| Message ID | 1565609303-27000-6-git-send-email-kyarlagadda@nvidia.com |
|---|---|
| State | Deferred |
| Headers | show |
| Series | serial: tegra: Tegra186 support and fixes | expand |
On Mon, Aug 12, 2019 at 04:58:14PM +0530, Krishna Yarlagadda wrote: > From: Shardar Shariff Md <smohammed@nvidia.com> > > FIFO reset/flush code implemented now does not follow programming > guidelines. RTS line has to be turned off while flushing fifos to > avoid new transfers. Also check LSR bits UART_LSR_TEMT and UART_LSR_DR > to confirm fifos are flushed. You use inconsistent spelling for FIFO here. > Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com> > Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com> > --- > drivers/tty/serial/serial-tegra.c | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) > > diff --git a/drivers/tty/serial/serial-tegra.c b/drivers/tty/serial/serial-tegra.c > index ae7225c..f6a3f4e 100644 > --- a/drivers/tty/serial/serial-tegra.c > +++ b/drivers/tty/serial/serial-tegra.c > @@ -266,6 +266,10 @@ static void tegra_uart_wait_sym_time(struct tegra_uart_port *tup, > static void tegra_uart_fifo_reset(struct tegra_uart_port *tup, u8 fcr_bits) > { > unsigned long fcr = tup->fcr_shadow; > + unsigned int lsr, tmout = 10000; > + > + if (tup->rts_active) > + set_rts(tup, false); > > if (tup->cdata->allow_txfifo_reset_fifo_mode) { > fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); > @@ -289,6 +293,17 @@ static void tegra_uart_fifo_reset(struct tegra_uart_port *tup, u8 fcr_bits) > * to propagate, otherwise data could be lost. > */ > tegra_uart_wait_cycle_time(tup, 32); > + > + do { > + lsr = tegra_uart_read(tup, UART_LSR); > + if (lsr | UART_LSR_TEMT) > + if (!(lsr & UART_LSR_DR)) Can't both of these go on the same line? Thierry > + break; > + udelay(1); > + } while (--tmout); > + > + if (tup->rts_active) > + set_rts(tup, true); > } > > static int tegra_set_baudrate(struct tegra_uart_port *tup, unsigned int baud) > -- > 2.7.4 >
> -----Original Message----- > From: Thierry Reding <thierry.reding@gmail.com> > Sent: Tuesday, August 13, 2019 3:19 PM > To: Krishna Yarlagadda <kyarlagadda@nvidia.com> > Cc: gregkh@linuxfoundation.org; robh+dt@kernel.org; > mark.rutland@arm.com; Jonathan Hunter <jonathanh@nvidia.com>; Laxman > Dewangan <ldewangan@nvidia.com>; jslaby@suse.com; linux- > serial@vger.kernel.org; devicetree@vger.kernel.org; linux- > tegra@vger.kernel.org; linux-kernel@vger.kernel.org; Shardar Mohammed > <smohammed@nvidia.com> > Subject: Re: [PATCH 05/14] serial: tegra: flush the RX fifo on frame error > > On Mon, Aug 12, 2019 at 04:58:14PM +0530, Krishna Yarlagadda wrote: > > From: Shardar Shariff Md <smohammed@nvidia.com> > > > > FIFO reset/flush code implemented now does not follow programming > > guidelines. RTS line has to be turned off while flushing fifos to > > avoid new transfers. Also check LSR bits UART_LSR_TEMT and > UART_LSR_DR > > to confirm fifos are flushed. > > You use inconsistent spelling for FIFO here. Will fix in next version and take care of this in all patches > > > Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com> > > Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com> > > --- > > drivers/tty/serial/serial-tegra.c | 15 +++++++++++++++ > > 1 file changed, 15 insertions(+) > > > > diff --git a/drivers/tty/serial/serial-tegra.c > > b/drivers/tty/serial/serial-tegra.c > > index ae7225c..f6a3f4e 100644 > > --- a/drivers/tty/serial/serial-tegra.c > > +++ b/drivers/tty/serial/serial-tegra.c > > @@ -266,6 +266,10 @@ static void tegra_uart_wait_sym_time(struct > > tegra_uart_port *tup, static void tegra_uart_fifo_reset(struct > > tegra_uart_port *tup, u8 fcr_bits) { > > unsigned long fcr = tup->fcr_shadow; > > + unsigned int lsr, tmout = 10000; > > + > > + if (tup->rts_active) > > + set_rts(tup, false); > > > > if (tup->cdata->allow_txfifo_reset_fifo_mode) { > > fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | > UART_FCR_CLEAR_XMIT); @@ > > -289,6 +293,17 @@ static void tegra_uart_fifo_reset(struct tegra_uart_port > *tup, u8 fcr_bits) > > * to propagate, otherwise data could be lost. > > */ > > tegra_uart_wait_cycle_time(tup, 32); > > + > > + do { > > + lsr = tegra_uart_read(tup, UART_LSR); > > + if (lsr | UART_LSR_TEMT) > > + if (!(lsr & UART_LSR_DR)) > > Can't both of these go on the same line? > > Thierry > They can be. Will fix in next version KY > > + break; > > + udelay(1); > > + } while (--tmout); > > + > > + if (tup->rts_active) > > + set_rts(tup, true); > > } > > > > static int tegra_set_baudrate(struct tegra_uart_port *tup, unsigned > > int baud) > > -- > > 2.7.4 > >
diff --git a/drivers/tty/serial/serial-tegra.c b/drivers/tty/serial/serial-tegra.c index ae7225c..f6a3f4e 100644 --- a/drivers/tty/serial/serial-tegra.c +++ b/drivers/tty/serial/serial-tegra.c @@ -266,6 +266,10 @@ static void tegra_uart_wait_sym_time(struct tegra_uart_port *tup, static void tegra_uart_fifo_reset(struct tegra_uart_port *tup, u8 fcr_bits) { unsigned long fcr = tup->fcr_shadow; + unsigned int lsr, tmout = 10000; + + if (tup->rts_active) + set_rts(tup, false); if (tup->cdata->allow_txfifo_reset_fifo_mode) { fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); @@ -289,6 +293,17 @@ static void tegra_uart_fifo_reset(struct tegra_uart_port *tup, u8 fcr_bits) * to propagate, otherwise data could be lost. */ tegra_uart_wait_cycle_time(tup, 32); + + do { + lsr = tegra_uart_read(tup, UART_LSR); + if (lsr | UART_LSR_TEMT) + if (!(lsr & UART_LSR_DR)) + break; + udelay(1); + } while (--tmout); + + if (tup->rts_active) + set_rts(tup, true); } static int tegra_set_baudrate(struct tegra_uart_port *tup, unsigned int baud)