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[3/3] dmaengine: tegra210-adma: Fix spelling

Message ID 1558022034-19911-4-git-send-email-jonathanh@nvidia.com
State Deferred
Headers show
Series dmaengine: tegra210-adma: Fixes for v5.2 | expand

Commit Message

Jon Hunter May 16, 2019, 3:53 p.m. UTC 
Correct spelling of 'register' in Tegra210 ADMA driver.

Fixes: ded1f3db4cd6 ("dmaengine: tegra210-adma: prepare for supporting newer Tegra chips")

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
---
 drivers/dma/tegra210-adma.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
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Patch

diff --git a/drivers/dma/tegra210-adma.c b/drivers/dma/tegra210-adma.c
index 3f50fd11c380..17ea4dd99c62 100644
--- a/drivers/dma/tegra210-adma.c
+++ b/drivers/dma/tegra210-adma.c
@@ -95,7 +95,7 @@  struct tegra_adma;
  * @global_int_clear: Register offset of DMA global interrupt clear.
  * @ch_req_tx_shift: Register offset for AHUB transmit channel select.
  * @ch_req_rx_shift: Register offset for AHUB receive channel select.
- * @ch_base_offset: Reister offset of DMA channel registers.
+ * @ch_base_offset: Register offset of DMA channel registers.
  * @ch_fifo_ctrl: Default value for channel FIFO CTRL register.
  * @ch_req_mask: Mask for Tx or Rx channel select.
  * @ch_req_max: Maximum number of Tx or Rx channels available.