From patchwork Tue Apr 16 16:48:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 1086426 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="ZjX4DTlG"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44kBBq6dL0z9s5c for ; Wed, 17 Apr 2019 02:48:19 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727052AbfDPQsT (ORCPT ); Tue, 16 Apr 2019 12:48:19 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:11728 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726860AbfDPQsS (ORCPT ); Tue, 16 Apr 2019 12:48:18 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 16 Apr 2019 09:48:13 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 16 Apr 2019 09:48:16 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 16 Apr 2019 09:48:16 -0700 Received: from HQMAIL103.nvidia.com (172.20.187.11) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 16 Apr 2019 16:48:16 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Tue, 16 Apr 2019 16:48:16 +0000 Received: from moonraker.nvidia.com (Not Verified[10.21.132.148]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 16 Apr 2019 09:48:16 -0700 From: Jon Hunter To: Thierry Reding CC: Sandipan Patra , , Jon Hunter Subject: [PATCH V2 1/3] soc/tegra: pmc: Fix reset sources and levels Date: Tue, 16 Apr 2019 17:48:06 +0100 Message-ID: <1555433288-16967-1-git-send-email-jonathanh@nvidia.com> X-Mailer: git-send-email 2.7.4 X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1555433294; bh=cUzKtfIg37MizuPX5yAgBzvb485MpLTgWj6qVjRcb18=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: X-NVConfidentiality:MIME-Version:Content-Type; b=ZjX4DTlGJ9c+0H0RIq5VMyfiFvspl/2ycZU/LJlNmXieYVKFxtgDVfDf0eHvC3QGu Ec1Tbq73srD3v6+CuArui3OssQKQ4kNKDxUbPHk/mpZxBSx3MYVkVsE6AK9VmNDCNu OHr2o+DQ0GoyqPO9Rf09kUB0tPd8Px+2drSoB++RMxstcgoHpPXP2Kal/Iy+XdsiYR rD1ISHcdMKxo55HDa2Ww+zOHiILJSxtzp0V/nna9HM94BhQSNXfrpMG4m6E+iHpTME MgncrGqnif5/CipPgTNn3mwr6m+4ITYIODMwGBDV2q9ZLqjTGTk0jjKzvwNsozAssA Ws/bU7FzvHSVg== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Commit 5f84bb1a4099 ("soc/tegra: pmc: Add sysfs entries for reset info") added support for reading the Tegra reset source and level from sysfs. However, there are a few issues with this commit which are ... 1. The number of reset sources for Tegra210 is defined as 5 but it should be 6. 2. The number of reset sources for Tegra186 is defined as 13 but it should be 15. 3. The SoC data variables num_reset_sources and num_reset_levels are defined but never used. Fix the above by ... 1. Removing the reset source 'AOTAG' from the tegra30_reset_sources because this is only applicable for Tegra210. 2. Adding a new tegra210_reset_sources structure for Tegra210 reset sources. 3. Correct the number of reset sources for Tegra210 and Tegra186 by using the ARRAY_SIZE macro. 4. Updating the functions reset_reason_show() and reset_level_show() to check whether the value read is valid. While we are at it clean-up these functions to remove an unnecessary u32 variable. Fixes: 5f84bb1a4099 ("soc/tegra: pmc: Add sysfs entries for reset info") Signed-off-by: Jon Hunter --- Changes since V1: - Reverted removal of num_reset_sources/levels - Used ARRAY_SIZE macro to populate num_reset_sources/levels - Added test to ensure that reset source/level is valid drivers/soc/tegra/pmc.c | 44 +++++++++++++++++++++++++++++--------------- 1 file changed, 29 insertions(+), 15 deletions(-) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index 0c5f79528e5f..7953aa7b11df 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -272,6 +272,14 @@ static const char * const tegra30_reset_sources[] = { "WATCHDOG", "SENSOR", "SW_MAIN", + "LP0" +}; + +static const char * const tegra210_reset_sources[] = { + "POWER_ON_RESET", + "WATCHDOG", + "SENSOR", + "SW_MAIN", "LP0", "AOTAG" }; @@ -1736,13 +1744,16 @@ static int tegra_pmc_pinctrl_init(struct tegra_pmc *pmc) static ssize_t reset_reason_show(struct device *dev, struct device_attribute *attr, char *buf) { - u32 value, rst_src; + u32 value; value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status); - rst_src = (value & pmc->soc->regs->rst_source_mask) >> - pmc->soc->regs->rst_source_shift; + value &= pmc->soc->regs->rst_source_mask; + value >>= pmc->soc->regs->rst_source_shift; + + if (WARN_ON(value >= pmc->soc->num_reset_sources)) + return sprintf(buf, "%s\n", "UNKNOWN"); - return sprintf(buf, "%s\n", pmc->soc->reset_sources[rst_src]); + return sprintf(buf, "%s\n", pmc->soc->reset_sources[value]); } static DEVICE_ATTR_RO(reset_reason); @@ -1750,13 +1761,16 @@ static DEVICE_ATTR_RO(reset_reason); static ssize_t reset_level_show(struct device *dev, struct device_attribute *attr, char *buf) { - u32 value, rst_lvl; + u32 value; value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status); - rst_lvl = (value & pmc->soc->regs->rst_level_mask) >> - pmc->soc->regs->rst_level_shift; + value &= pmc->soc->regs->rst_level_mask; + value >>= pmc->soc->regs->rst_level_shift; - return sprintf(buf, "%s\n", pmc->soc->reset_levels[rst_lvl]); + if (WARN_ON(value >= pmc->soc->num_reset_levels)) + return sprintf(buf, "%s\n", "UNKNOWN"); + + return sprintf(buf, "%s\n", pmc->soc->reset_levels[value]); } static DEVICE_ATTR_RO(reset_level); @@ -2212,7 +2226,7 @@ static const struct tegra_pmc_soc tegra30_pmc_soc = { .init = tegra20_pmc_init, .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, .reset_sources = tegra30_reset_sources, - .num_reset_sources = 5, + .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources), .reset_levels = NULL, .num_reset_levels = 0, }; @@ -2263,7 +2277,7 @@ static const struct tegra_pmc_soc tegra114_pmc_soc = { .init = tegra20_pmc_init, .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, .reset_sources = tegra30_reset_sources, - .num_reset_sources = 5, + .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources), .reset_levels = NULL, .num_reset_levels = 0, }; @@ -2374,7 +2388,7 @@ static const struct tegra_pmc_soc tegra124_pmc_soc = { .init = tegra20_pmc_init, .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, .reset_sources = tegra30_reset_sources, - .num_reset_sources = 5, + .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources), .reset_levels = NULL, .num_reset_levels = 0, }; @@ -2479,8 +2493,8 @@ static const struct tegra_pmc_soc tegra210_pmc_soc = { .regs = &tegra20_pmc_regs, .init = tegra20_pmc_init, .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, - .reset_sources = tegra30_reset_sources, - .num_reset_sources = 5, + .reset_sources = tegra210_reset_sources, + .num_reset_sources = ARRAY_SIZE(tegra210_reset_sources), .reset_levels = NULL, .num_reset_levels = 0, }; @@ -2605,9 +2619,9 @@ static const struct tegra_pmc_soc tegra186_pmc_soc = { .init = NULL, .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, .reset_sources = tegra186_reset_sources, - .num_reset_sources = 14, + .num_reset_sources = ARRAY_SIZE(tegra186_reset_sources), .reset_levels = tegra186_reset_levels, - .num_reset_levels = 3, + .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels), .num_wake_events = ARRAY_SIZE(tegra186_wake_events), .wake_events = tegra186_wake_events, };