From patchwork Wed Sep 26 12:27:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 975055 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="B1iMeDVV"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42Kxzm3rTTz9s1c for ; Wed, 26 Sep 2018 22:28:04 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727549AbeIZSkm (ORCPT ); Wed, 26 Sep 2018 14:40:42 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:8729 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726880AbeIZSkl (ORCPT ); Wed, 26 Sep 2018 14:40:41 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Wed, 26 Sep 2018 05:28:02 -0700 Received: from HQMAIL106.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Wed, 26 Sep 2018 05:27:56 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Wed, 26 Sep 2018 05:27:56 -0700 Received: from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 26 Sep 2018 12:27:55 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Wed, 26 Sep 2018 12:27:55 +0000 Received: from moonraker.nvidia.com (Not Verified[10.21.132.143]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Wed, 26 Sep 2018 05:27:55 -0700 From: Jon Hunter To: Rob Herring , Mark Rutland , "Rafael J . Wysocki" , Kevin Hilman , Ulf Hansson , Greg Kroah-Hartman , Mathias Nyman , Thierry Reding CC: , , , Jon Hunter Subject: [PATCH 5/5] arm64: dts: tegra210: Add power-domains for xHCI Date: Wed, 26 Sep 2018 13:27:38 +0100 Message-ID: <1537964858-30332-6-git-send-email-jonathanh@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1537964858-30332-1-git-send-email-jonathanh@nvidia.com> References: <1537964858-30332-1-git-send-email-jonathanh@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1537964882; bh=A5+LaSIS2MtAbQ6Lm1NQ7m3punvjkIxzOXDsA/lzCpo=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=B1iMeDVVdOnmP13Sf3GIS2mFOtDfLOYBUD3rr+TwU/zyL3JGXYSOMvzCupVApcW05 ucoF9ZmD2NRan+4B3uV1DiwGJ5Ptv50+82di9vZXnq/O8zfARM/RwvXX1OklWVVp26 VfDt5sdEqfpvMRa3Vi1U6puPLfiU2yc699EjI7/NwVNMG2FR4awqneT0k/qtv4RT3W nCoVv48ojxrFSN/oNfA2BF6zHUWAdR6/I1eP8c2Q1YhyjGxuYnStZQhe8Ktmz7dA4D jOOfsdRAimxPSFvC3XocoD/zZHQ6Lh/4c598KH2iCXXCHDfRnv9QBdSr/75MMqat4M yxi/AQn8CLwcw== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Populate the power-domain properties for the xHCI device for Tegra210. Signed-off-by: Jon Hunter --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 8fe47d6445a5..2205d66b0443 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -879,6 +879,8 @@ resets = <&tegra_car 89>, <&tegra_car 156>, <&tegra_car 143>; reset-names = "xusb_host", "xusb_ss", "xusb_src"; + power-domains = <&pd_xusbhost>, <&pd_xusbss>; + power-domain-names = "xusb_host", "xusb_ss"; nvidia,xusb-padctl = <&padctl>;