Message ID | 1532339619-12162-1-git-send-email-jonathanh@nvidia.com |
---|---|
State | Deferred |
Headers | show |
Series | stable request: 4.4.y: 797097301860 ("clk: tegra: Fix PLL_U post divider and initial rate on Tegra30") | expand |
On 23/07/18 10:53, Jon Hunter wrote: > Please include the following fix for stable v4.4.y. If the PLL_U is not > configured by the bootloader, then without this change it will not be > configured by the kernel and this will cause USB host support to fail > which uses the PLL_U for its clock. > > Please note that this patch did not apply cleanly to v4.4.y, so I have > back-ported, but the resulting change is the same as the original. > >>From 797097301860c64b63346d068ba4fe4992bd5021 Mon Sep 17 00:00:00 2001 > From: Lucas Stach <dev@lynxeye.de> > Date: Mon, 29 Feb 2016 21:46:07 +0100 > Subject: [PATCH] clk: tegra: Fix PLL_U post divider and initial rate on > Tegra30 I am resending this as I missed the 'commit <sha1> upstream' tag. Jon
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index 8c41c6fcb9ee..acf83569f86f 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -333,11 +333,11 @@ static struct pdiv_map pllu_p[] = { }; static struct tegra_clk_pll_freq_table pll_u_freq_table[] = { - { 12000000, 480000000, 960, 12, 0, 12}, - { 13000000, 480000000, 960, 13, 0, 12}, - { 16800000, 480000000, 400, 7, 0, 5}, - { 19200000, 480000000, 200, 4, 0, 3}, - { 26000000, 480000000, 960, 26, 0, 12}, + { 12000000, 480000000, 960, 12, 2, 12 }, + { 13000000, 480000000, 960, 13, 2, 12 }, + { 16800000, 480000000, 400, 7, 2, 5 }, + { 19200000, 480000000, 200, 4, 2, 3 }, + { 26000000, 480000000, 960, 26, 2, 12 }, { 0, 0, 0, 0, 0, 0 }, }; @@ -1372,6 +1372,7 @@ static struct tegra_clk_init_table init_table[] __initdata = { {TEGRA30_CLK_GR2D, TEGRA30_CLK_PLL_C, 300000000, 0}, {TEGRA30_CLK_GR3D, TEGRA30_CLK_PLL_C, 300000000, 0}, {TEGRA30_CLK_GR3D2, TEGRA30_CLK_PLL_C, 300000000, 0}, + { TEGRA30_CLK_PLL_U, TEGRA30_CLK_CLK_MAX, 480000000, 0 }, {TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_CLK_MAX, 0, 0}, /* This MUST be the last entry. */ };