From patchwork Mon Oct 23 14:35:07 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 829320 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yLJrb3YPYz9t6F for ; Tue, 24 Oct 2017 01:37:03 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932394AbdJWOhC (ORCPT ); Mon, 23 Oct 2017 10:37:02 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:11667 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932387AbdJWOhB (ORCPT ); Mon, 23 Oct 2017 10:37:01 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Mon, 23 Oct 2017 07:36:33 -0700 Received: from HQMAIL105.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 23 Oct 2017 07:36:51 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 23 Oct 2017 07:36:51 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Mon, 23 Oct 2017 14:35:24 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server id 15.0.1293.2 via Frontend Transport; Mon, 23 Oct 2017 14:35:24 +0000 Received: from vidyas-desktop.nvidia.com (Not Verified[10.24.36.185]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Mon, 23 Oct 2017 07:35:24 -0700 From: Vidya Sagar To: , CC: , , , , , , Subject: [PATCH V2 2/7] ARM: tegra: limit PCIe config space mapping to 4K for T20 Date: Mon, 23 Oct 2017 20:05:07 +0530 Message-ID: <1508769312-12465-3-git-send-email-vidyas@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1508769312-12465-1-git-send-email-vidyas@nvidia.com> References: <1508769312-12465-1-git-send-email-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org reduces PCIe end point config space mapping size from its current 256MB to 4K to give more space for BAR mapping Signed-off-by: Vidya Sagar --- V2: * no changes in this patch arch/arm/boot/dts/tegra20.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 7c85f97f72ea..4c761a60cdf7 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -591,7 +591,7 @@ device_type = "pci"; reg = <0x80003000 0x00000800 /* PADS registers */ 0x80003800 0x00000200 /* AFI registers */ - 0x90000000 0x10000000>; /* configuration space */ + 0x82000000 0x00001000>; /* configuration space */ reg-names = "pads", "afi", "cs"; interrupts = ; /* MSI interrupt */ @@ -607,9 +607,9 @@ ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000 /* port 0 registers */ 0x82000000 0 0x80001000 0x80001000 0 0x00001000 /* port 1 registers */ - 0x81000000 0 0 0x82000000 0 0x00010000 /* downstream I/O */ - 0x82000000 0 0xa0000000 0xa0000000 0 0x08000000 /* non-prefetchable memory */ - 0xc2000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */ + 0x81000000 0 0 0x82001000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x82100000 0x82100000 0 0x05F00000 /* non-prefetchable memory */ + 0xc2000000 0 0x88000000 0x88000000 0 0x38000000>; /* prefetchable memory */ clocks = <&tegra_car TEGRA20_CLK_PEX>, <&tegra_car TEGRA20_CLK_AFI>,