Message ID | 1507834211-24922-4-git-send-email-vidyas@nvidia.com |
---|---|
State | Superseded |
Headers | show |
Series | Tegra PCIe end point config space map code refactoring | expand |
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 13960fda7471..b23171f2b86f 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -15,7 +15,7 @@ device_type = "pci"; reg = <0x00003000 0x00000800 /* PADS registers */ 0x00003800 0x00000200 /* AFI registers */ - 0x10000000 0x10000000>; /* configuration space */ + 0x1FFFF000 0x00001000>; /* configuration space */ reg-names = "pads", "afi", "cs"; interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */ GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
reduces PCIe config space mapping size from its current 256MB to 4K to have only 4K of virtual memory mapping and to be in line with driver implementation Signed-off-by: Vidya Sagar <vidyas@nvidia.com> --- arch/arm/boot/dts/tegra30.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)