From patchwork Tue Mar 28 11:48:38 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 744215 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3vsq1M19m5z9s76 for ; Tue, 28 Mar 2017 22:49:11 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751553AbdC1Lsv (ORCPT ); Tue, 28 Mar 2017 07:48:51 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:17891 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751459AbdC1Lsp (ORCPT ); Tue, 28 Mar 2017 07:48:45 -0400 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Tue, 28 Mar 2017 04:48:23 -0700 Received: from HQMAIL104.nvidia.com ([172.20.13.39]) by hqnvupgp08.nvidia.com (PGP Universal service); Tue, 28 Mar 2017 04:45:30 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Tue, 28 Mar 2017 04:45:30 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1263.5; Tue, 28 Mar 2017 11:48:43 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server id 15.0.1263.5 via Frontend Transport; Tue, 28 Mar 2017 11:48:43 +0000 Received: from goldfinger.nvidia.com (Not Verified[10.21.132.162]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 5, 8150) id ; Tue, 28 Mar 2017 04:48:43 -0700 From: Jon Hunter To: Thierry Reding , Stephen Warren CC: , , , Martin Michlmayr , Vagrant Cascadian , Jon Hunter Subject: [PATCH] arm64: tegra: Add CPU and PSCI nodes for NVIDIA Tegra210 platforms Date: Tue, 28 Mar 2017 12:48:38 +0100 Message-ID: <1490701718-16571-1-git-send-email-jonathanh@nvidia.com> X-Mailer: git-send-email 2.7.4 X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Add the CPU and PSCI nodes for the NVIDIA Tegra210 platforms so that all CPUs can be enabled on boot. This assumes that the PSCI firmware has been loaded during the initial bootstrap on the device before the kernel starts (which is typically the case for these platforms). The PSCI firmware version is set to v0.2 which aligns with the current shipping version for Tegra. Reported-by: Martin Michlmayr Signed-off-by: Jon Hunter Tested-By: Vagrant Cascadian --- arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 23 +++++++++++++++++++++++ arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi | 24 ++++++++++++++++++++++++ 2 files changed, 47 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi index 906fb836d241..de1696c28140 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi @@ -296,6 +296,29 @@ }; }; + cpus { + cpu@0 { + enable-method = "psci"; + }; + + cpu@1 { + enable-method = "psci"; + }; + + cpu@2 { + enable-method = "psci"; + }; + + cpu@3 { + enable-method = "psci"; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + regulators { vdd_gpu: regulator@100 { compatible = "pwm-regulator"; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi index 0ec92578cacb..67cb039965fd 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi @@ -51,4 +51,28 @@ clock-frequency = <32768>; }; }; + + cpus { + cpu@0 { + enable-method = "psci"; + }; + + cpu@1 { + enable-method = "psci"; + }; + + cpu@2 { + enable-method = "psci"; + }; + + cpu@3 { + enable-method = "psci"; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + };