From patchwork Tue Jun 28 11:20:44 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 641501 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3rf3K43M7Fz9snl for ; Tue, 28 Jun 2016 21:21:12 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752436AbcF1LUy (ORCPT ); Tue, 28 Jun 2016 07:20:54 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:15471 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752367AbcF1LUx (ORCPT ); Tue, 28 Jun 2016 07:20:53 -0400 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Tue, 28 Jun 2016 04:20:19 -0700 Received: from HQMAIL103.nvidia.com ([172.20.187.11]) by hqnvupgp08.nvidia.com (PGP Universal service); Tue, 28 Jun 2016 04:19:40 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Tue, 28 Jun 2016 04:19:40 -0700 Received: from HQMAIL104.nvidia.com (172.18.146.11) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1130.7; Tue, 28 Jun 2016 11:20:52 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server id 15.0.1130.7 via Frontend Transport; Tue, 28 Jun 2016 11:20:52 +0000 Received: from jonathanh-lm.nvidia.com (Not Verified[10.21.132.149]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 5, 8150) id ; Tue, 28 Jun 2016 04:20:52 -0700 From: Jon Hunter To: Stephen Warren , Thierry Reding , Alexandre Courbot CC: , , Jon Hunter Subject: [RFC PATCH 3/3] arm64: tegra210: Add XUSB powergates Date: Tue, 28 Jun 2016 12:20:44 +0100 Message-ID: <1467112844-26927-4-git-send-email-jonathanh@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1467112844-26927-1-git-send-email-jonathanh@nvidia.com> References: <1467112844-26927-1-git-send-email-jonathanh@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The Tegra210 XUSB subsystem has 3 power partitions which are XUSBA (super-speed logic), XUSBB (USB device logic) and XUSBC (USB host logic). Populate the device-tree nodes for these XUSB partitions. Signed-off-by: Jon Hunter --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 65b829b762bb..efb0fd98b789 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -670,6 +670,30 @@ <&tegra_car TEGRA210_CLK_MIPI_CAL>; #power-domain-cells = <0>; }; + + pd_xusbss: xusba { + clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; + clock-names = "xusb_ss"; + resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; + reset-names = "xusb_ss"; + #power-domain-cells = <0>; + }; + + pd_xusbdev: xusbb { + clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>; + clock-names = "xusb_dev"; + resets = <&tegra_car 95>; + reset-names = "xusb_dev"; + #power-domain-cells = <0>; + }; + + pd_xusbhost: xusbc { + clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>; + clock-names = "xusb_host"; + resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>; + reset-names = "xusb_host"; + #power-domain-cells = <0>; + }; }; };