From patchwork Wed Jun 22 11:47:21 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laxman Dewangan X-Patchwork-Id: 639132 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3rZNVw6BYQz9t0Y for ; Wed, 22 Jun 2016 22:02:00 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752657AbcFVMBQ (ORCPT ); Wed, 22 Jun 2016 08:01:16 -0400 Received: from nat-hk.nvidia.com ([203.18.50.4]:58246 "EHLO hkmmgate101.nvidia.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752646AbcFVMBN (ORCPT ); Wed, 22 Jun 2016 08:01:13 -0400 Received: from hkpgpgate102.nvidia.com (Not Verified[10.18.92.9]) by hkmmgate101.nvidia.com id ; Wed, 22 Jun 2016 20:01:11 +0800 Received: from HKMAIL101.nvidia.com ([10.18.67.137]) by hkpgpgate102.nvidia.com (PGP Universal service); Wed, 22 Jun 2016 05:01:09 -0700 X-PGP-Universal: processed; by hkpgpgate102.nvidia.com on Wed, 22 Jun 2016 05:01:09 -0700 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HKMAIL101.nvidia.com (10.18.16.10) with Microsoft SMTP Server (TLS) id 15.0.1130.7; Wed, 22 Jun 2016 12:01:07 +0000 Received: from ldewanganubuntu-System-Product-Name.nvidia.com (172.20.13.39) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server id 15.0.1130.7 via Frontend Transport; Wed, 22 Jun 2016 12:01:03 +0000 From: Laxman Dewangan To: , , , CC: , , , , Hyong Bin Kim , Laxman Dewangan Subject: [PATCH 3/5] pwm: tegra: fix overflow when calculating duty cycle Date: Wed, 22 Jun 2016 17:17:21 +0530 Message-ID: <1466596043-27262-4-git-send-email-ldewangan@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1466596043-27262-1-git-send-email-ldewangan@nvidia.com> References: <1466596043-27262-1-git-send-email-ldewangan@nvidia.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Hyong Bin Kim duty_ns * (1 << PWM_DUTY_WIDTH) could overflow in integer calcualtion when PWM rate is low. Hence do all calculation on unsigned long long to avoid overflow. Signed-off-by: Hyong Bin Kim Signed-off-by: Laxman Dewangan --- drivers/pwm/pwm-tegra.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c index 575ca8e..49cefd5 100644 --- a/drivers/pwm/pwm-tegra.c +++ b/drivers/pwm/pwm-tegra.c @@ -69,7 +69,7 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, int duty_ns, int period_ns) { struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip); - unsigned long long c; + unsigned long long c = duty_ns; unsigned long rate, hz; u32 val = 0; int err; @@ -79,7 +79,8 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, * per (1 << PWM_DUTY_WIDTH) cycles and make sure to round to the * nearest integer during division. */ - c = duty_ns * (1 << PWM_DUTY_WIDTH) + period_ns / 2; + c *= (1 << PWM_DUTY_WIDTH); + c += period_ns / 2; do_div(c, period_ns); val = (u32)c << PWM_DUTY_SHIFT;