From patchwork Fri Apr 22 10:31:02 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Penny Chiu X-Patchwork-Id: 613534 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3qrsT55cYkz9t0t for ; Fri, 22 Apr 2016 20:35:21 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752190AbcDVKcR (ORCPT ); Fri, 22 Apr 2016 06:32:17 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:16349 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751172AbcDVKcO (ORCPT ); Fri, 22 Apr 2016 06:32:14 -0400 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Fri, 22 Apr 2016 03:32:04 -0700 Received: from HQMAIL107.nvidia.com ([172.20.187.13]) by hqnvupgp07.nvidia.com (PGP Universal service); Fri, 22 Apr 2016 03:32:03 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Fri, 22 Apr 2016 03:32:03 -0700 Received: from HQMAIL106.nvidia.com (172.18.146.12) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1130.7; Fri, 22 Apr 2016 10:32:12 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server id 15.0.1130.7 via Frontend Transport; Fri, 22 Apr 2016 10:32:12 +0000 Received: from pchiu-i7.nvidia.com (Not Verified[10.19.120.104]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 5, 8150) id ; Fri, 22 Apr 2016 03:32:12 -0700 From: Penny Chiu To: , , , , , , CC: , , , , , , , , Penny Chiu Subject: [PATCH 02/11] clk: tegra: dfll: Move SoC specific data into of_device_id Date: Fri, 22 Apr 2016 18:31:02 +0800 Message-ID: <1461321071-6431-3-git-send-email-pchiu@nvidia.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1461321071-6431-1-git-send-email-pchiu@nvidia.com> References: <1461321071-6431-1-git-send-email-pchiu@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Move all SoC specific fcpu data into of_device_id structure, and move SoC fcpu data assignments from init function to probe function. Signed-off-by: Penny Chiu --- drivers/clk/tegra/clk-tegra124-dfll-fcpu.c | 51 ++++++++++++++++++++++-------- 1 file changed, 37 insertions(+), 14 deletions(-) diff --git a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c index 5e5958e..b577bc6 100644 --- a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c +++ b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include @@ -28,8 +29,15 @@ #include "clk-dfll.h" #include "cvb.h" +struct dfll_fcpu_data { + const unsigned long *cpu_max_freq_table; + unsigned int cpu_max_freq_table_size; + const struct cvb_table *cpu_cvb_tables; + unsigned int cpu_cvb_tables_size; +}; + /* Maximum CPU frequency, indexed by CPU speedo id */ -static const unsigned long cpu_max_freq_table[] = { +static const unsigned long tegra124_cpu_max_freq_table[] = { [0] = 2014500000UL, [1] = 2320500000UL, [2] = 2116500000UL, @@ -79,18 +87,39 @@ static const struct cvb_table tegra124_cpu_cvb_tables[] = { }, }; +static const struct dfll_fcpu_data tegra124_dfll_fcpu_data = { + .cpu_max_freq_table = tegra124_cpu_max_freq_table, + .cpu_max_freq_table_size = ARRAY_SIZE(tegra124_cpu_max_freq_table), + .cpu_cvb_tables = tegra124_cpu_cvb_tables, + .cpu_cvb_tables_size = ARRAY_SIZE(tegra124_cpu_cvb_tables) +}; + +static const struct of_device_id tegra124_dfll_fcpu_of_match[] = { + { + .compatible = "nvidia,tegra124-dfll", + .data = &tegra124_dfll_fcpu_data + }, + { }, +}; +MODULE_DEVICE_TABLE(of, tegra124_dfll_fcpu_of_match); + static int tegra124_dfll_fcpu_probe(struct platform_device *pdev) { int process_id, speedo_id, speedo_value, ret; struct rail_alignment align; struct tegra_dfll_soc_data *soc; const struct cvb_table *cvb; + const struct of_device_id *of_id; + const struct dfll_fcpu_data *fcpu_data; + + of_id = of_match_device(tegra124_dfll_fcpu_of_match, &pdev->dev); + fcpu_data = of_id->data; process_id = tegra_sku_info.cpu_process_id; speedo_id = tegra_sku_info.cpu_speedo_id; speedo_value = tegra_sku_info.cpu_speedo_value; - if (speedo_id >= ARRAY_SIZE(cpu_max_freq_table)) { + if (speedo_id >= fcpu_data->cpu_max_freq_table_size) { dev_err(&pdev->dev, "unknown max CPU freq for speedo_id=%d\n", speedo_id); return -ENODEV; @@ -121,12 +150,12 @@ static int tegra124_dfll_fcpu_probe(struct platform_device *pdev) return -EINVAL; } - cvb = tegra_cvb_build_opp_table(tegra124_cpu_cvb_tables, - ARRAY_SIZE(tegra124_cpu_cvb_tables), - &align, - process_id, speedo_id, speedo_value, - cpu_max_freq_table[speedo_id], - soc->dev); + cvb = tegra_cvb_build_opp_table(fcpu_data->cpu_cvb_tables, + fcpu_data->cpu_cvb_tables_size, + &align, + process_id, speedo_id, speedo_value, + fcpu_data->cpu_max_freq_table[speedo_id], + soc->dev); if (IS_ERR(cvb)) { dev_err(&pdev->dev, "couldn't build OPP table: %ld\n", PTR_ERR(cvb)); @@ -142,12 +171,6 @@ static int tegra124_dfll_fcpu_probe(struct platform_device *pdev) return tegra_dfll_register(pdev, soc); } -static const struct of_device_id tegra124_dfll_fcpu_of_match[] = { - { .compatible = "nvidia,tegra124-dfll", }, - { }, -}; -MODULE_DEVICE_TABLE(of, tegra124_dfll_fcpu_of_match); - static const struct dev_pm_ops tegra124_dfll_pm_ops = { SET_RUNTIME_PM_OPS(tegra_dfll_runtime_suspend, tegra_dfll_runtime_resume, NULL)