From patchwork Wed Nov 11 19:50:47 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan Wu X-Patchwork-Id: 543066 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 7A5B71402D4 for ; Thu, 12 Nov 2015 06:50:58 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752584AbbKKTuv (ORCPT ); Wed, 11 Nov 2015 14:50:51 -0500 Received: from hqemgate16.nvidia.com ([216.228.121.65]:16810 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752468AbbKKTuu (ORCPT ); Wed, 11 Nov 2015 14:50:50 -0500 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Wed, 11 Nov 2015 11:50:15 -0800 Received: from hqemhub03.nvidia.com ([172.20.12.94]) by hqnvupgp07.nvidia.com (PGP Universal service); Wed, 11 Nov 2015 11:39:45 -0800 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Wed, 11 Nov 2015 11:39:45 -0800 Received: from nvidia.com (172.20.144.16) by hqemhub03.nvidia.com (172.20.150.15) with Microsoft SMTP Server id 8.3.342.0; Wed, 11 Nov 2015 11:50:49 -0800 From: Bryan Wu To: , , , CC: , , , , Subject: [PATCH 2/3] ARM64: add tegra-vi support in T210 device-tree Date: Wed, 11 Nov 2015 11:50:47 -0800 Message-ID: <1447271448-30056-3-git-send-email-pengw@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1447271448-30056-1-git-send-email-pengw@nvidia.com> References: <1447271448-30056-1-git-send-email-pengw@nvidia.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Following device tree support for Tegra VI now: - "vi" node which might have 6 ports/endpoints - in TPG mode, "vi" node don't need to define any ports/endpoints - ports/endpoints defines the link between VI and external sensors. Signed-off-by: Bryan Wu --- arch/arm64/boot/dts/nvidia/tegra210-p2571.dts | 8 ++ arch/arm64/boot/dts/nvidia/tegra210.dtsi | 174 +++++++++++++++++++++++++- 2 files changed, 181 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2571.dts b/arch/arm64/boot/dts/nvidia/tegra210-p2571.dts index 50a3582..c573546 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2571.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2571.dts @@ -7,6 +7,14 @@ model = "NVIDIA Tegra210 P2571 reference board"; compatible = "nvidia,p2571", "nvidia,tegra210"; + host1x@0,50000000 { + vi@0,54080000 { + status = "okay"; + + avdd-dsi-csi-supply = <&vdd_dsi_csi>; + }; + }; + pinmux: pinmux@0,700008d4 { pinctrl-names = "boot"; pinctrl-0 = <&state_boot>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 8048fc5..57ffc28 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -123,9 +123,181 @@ vi@0,54080000 { compatible = "nvidia,tegra210-vi"; - reg = <0x0 0x54080000 0x0 0x00040000>; + reg = <0x0 0x54080000 0x0 0x800>; interrupts = ; status = "disabled"; + clocks = <&tegra_car TEGRA210_CLK_VI>, + <&tegra_car TEGRA210_CLK_CSI>, + <&tegra_car TEGRA210_CLK_PLL_C>; + clock-names = "vi", "csi", "parent"; + resets = <&tegra_car 20>; + reset-names = "vi"; + + power-domains = <&pmc TEGRA_POWERGATE_VENC>; + + iommus = <&mc TEGRA_SWGROUP_VI>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + vi_in0: endpoint { + remote-endpoint = <&csi_out0>; + }; + }; + port@1 { + reg = <1>; + + vi_in1: endpoint { + remote-endpoint = <&csi_out1>; + }; + }; + port@2 { + reg = <2>; + + vi_in2: endpoint { + remote-endpoint = <&csi_out2>; + }; + }; + port@3 { + reg = <3>; + + vi_in3: endpoint { + remote-endpoint = <&csi_out3>; + }; + }; + port@4 { + reg = <4>; + + vi_in4: endpoint { + remote-endpoint = <&csi_out4>; + }; + }; + port@5 { + reg = <5>; + + vi_in5: endpoint { + remote-endpoint = <&csi_out5>; + }; + }; + + }; + }; + + csi@0,54080838 { + compatible = "nvidia,tegra210-csi"; + reg = <0x0 0x54080838 0x0 0x700>; + clocks = <&tegra_car TEGRA210_CLK_CILAB>; + clock-names = "cil"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + csi_in0: endpoint@0 { + reg = <0x0>; + }; + csi_out0: endpoint@1 { + reg = <0x1>; + remote-endpoint = <&vi_in0>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + csi_in1: endpoint@0 { + reg = <0>; + }; + csi_out1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vi_in1>; + }; + }; + }; + }; + + csi@1,54081038 { + compatible = "nvidia,tegra210-csi"; + reg = <0x0 0x54081038 0x0 0x700>; + clocks = <&tegra_car TEGRA210_CLK_CILCD>; + clock-names = "cil"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + csi_in2: endpoint@0 { + reg = <0>; + }; + + csi_out2: endpoint@1 { + reg = <1>; + remote-endpoint = <&vi_in2>; + }; + }; + port@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + csi_in3: endpoint@0 { + reg = <0>; + }; + + csi_out3: endpoint@1 { + reg = <1>; + remote-endpoint = <&vi_in3>; + }; + }; + }; + }; + + csi@2,54081838 { + compatible = "nvidia,tegra210-csi"; + reg = <0x0 0x54081838 0x0 0x700>; + clocks = <&tegra_car TEGRA210_CLK_CILE>; + clock-names = "cil"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@4 { + reg = <4>; + #address-cells = <1>; + #size-cells = <0>; + csi_in4: endpoint@0 { + reg = <0>; + }; + csi_out4: endpoint@1 { + reg = <1>; + remote-endpoint = <&vi_in4>; + }; + }; + port@5 { + reg = <5>; + #address-cells = <1>; + #size-cells = <0>; + csi_in5: endpoint@0 { + reg = <0>; + }; + csi_out5: endpoint@1 { + reg = <1>; + remote-endpoint = <&vi_in5>; + }; + }; + }; }; tsec@0,54100000 {