From patchwork Mon Oct 26 11:02:14 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 535833 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 7435B1412FD for ; Mon, 26 Oct 2015 22:06:52 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753803AbbJZLGi (ORCPT ); Mon, 26 Oct 2015 07:06:38 -0400 Received: from mx0b-0016f401.pphosted.com ([67.231.156.173]:54294 "EHLO mx0b-0016f401.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753800AbbJZLGg (ORCPT ); Mon, 26 Oct 2015 07:06:36 -0400 Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.15.0.59/8.15.0.59) with SMTP id t9QB5H4I001513; Mon, 26 Oct 2015 04:06:01 -0700 Received: from sc-exch02.marvell.com ([199.233.58.182]) by mx0b-0016f401.pphosted.com with ESMTP id 1xsjh2829k-1 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Mon, 26 Oct 2015 04:06:01 -0700 Received: from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH02.marvell.com (10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1044.25; Mon, 26 Oct 2015 04:05:59 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server id 15.0.1044.25 via Frontend Transport; Mon, 26 Oct 2015 04:05:59 -0700 Received: from xhacker.marvell.com (unknown [10.37.135.134]) by maili.marvell.com (Postfix) with ESMTP id 358ED3F703F; Mon, 26 Oct 2015 04:05:57 -0700 (PDT) From: Jisheng Zhang To: , , , , , , , CC: , , , , , Jisheng Zhang Subject: [RFC PATCH 3/3] PCI: xgene: generate proper configuration access cycles Date: Mon, 26 Oct 2015 19:02:14 +0800 Message-ID: <1445857334-6936-4-git-send-email-jszhang@marvell.com> X-Mailer: git-send-email 2.6.2 In-Reply-To: <1445857334-6936-1-git-send-email-jszhang@marvell.com> References: <1445857334-6936-1-git-send-email-jszhang@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2015-10-26_09:, , signatures=0 X-Proofpoint-Spam-Details: rule=inbound_notspam policy=inbound score=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1507310000 definitions=main-1510260190 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Inspired by Russell King's patch[1], I found current tegra also has the same issue of "reading 32-bits from the command register, modifying the command register, and then writing it back has the effect of clearing any status bits that were indicating at that time" as pointed out by Russell. This patch fix this issue by using the pci_generic_config_write. [1]http://www.spinics.net/lists/linux-pci/msg44869.html Signed-off-by: Jisheng Zhang --- drivers/pci/host/pci-xgene.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/host/pci-xgene.c b/drivers/pci/host/pci-xgene.c index 0236ab9..8946a6c 100644 --- a/drivers/pci/host/pci-xgene.c +++ b/drivers/pci/host/pci-xgene.c @@ -176,7 +176,7 @@ static int xgene_pcie_config_read32(struct pci_bus *bus, unsigned int devfn, static struct pci_ops xgene_pcie_ops = { .map_bus = xgene_pcie_map_bus, .read = xgene_pcie_config_read32, - .write = pci_generic_config_write32, + .write = pci_generic_config_write, }; static u64 xgene_pcie_set_ib_mask(void __iomem *csr_base, u32 addr,