From patchwork Mon Oct 26 11:02:12 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 535836 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id D7EDC1412FD for ; Mon, 26 Oct 2015 22:07:37 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753673AbbJZLGa (ORCPT ); Mon, 26 Oct 2015 07:06:30 -0400 Received: from mx0a-0016f401.pphosted.com ([67.231.148.174]:51621 "EHLO mx0a-0016f401.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753619AbbJZLG2 (ORCPT ); Mon, 26 Oct 2015 07:06:28 -0400 Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.15.0.59/8.15.0.59) with SMTP id t9QB55kd004693; Mon, 26 Oct 2015 04:05:55 -0700 Received: from sc-exch04.marvell.com ([199.233.58.184]) by mx0a-0016f401.pphosted.com with ESMTP id 1xsjg6g2ba-1 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Mon, 26 Oct 2015 04:05:55 -0700 Received: from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH04.marvell.com (10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1044.25; Mon, 26 Oct 2015 04:05:54 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server id 15.0.1044.25 via Frontend Transport; Mon, 26 Oct 2015 04:05:54 -0700 Received: from xhacker.marvell.com (unknown [10.37.135.134]) by maili.marvell.com (Postfix) with ESMTP id 5D1393F7040; Mon, 26 Oct 2015 04:05:52 -0700 (PDT) From: Jisheng Zhang To: , , , , , , , CC: , , , , , Jisheng Zhang Subject: [RFC PATCH 1/3] PCI: iproc: generate proper configuration access cycles Date: Mon, 26 Oct 2015 19:02:12 +0800 Message-ID: <1445857334-6936-2-git-send-email-jszhang@marvell.com> X-Mailer: git-send-email 2.6.2 In-Reply-To: <1445857334-6936-1-git-send-email-jszhang@marvell.com> References: <1445857334-6936-1-git-send-email-jszhang@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2015-10-26_09:, , signatures=0 X-Proofpoint-Spam-Details: rule=inbound_notspam policy=inbound score=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1507310000 definitions=main-1510260190 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Inspired by Russell King's patch[1], I found current iproc also has the same issue of "reading 32-bits from the command register, modifying the command register, and then writing it back has the effect of clearing any status bits that were indicating at that time" as pointed out by Russell. This patch fix this issue by using the pci_generic_config_write. [1]http://www.spinics.net/lists/linux-pci/msg44869.html Signed-off-by: Jisheng Zhang --- drivers/pci/host/pcie-iproc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/host/pcie-iproc.c b/drivers/pci/host/pcie-iproc.c index fe2efb1..0c423f2 100644 --- a/drivers/pci/host/pcie-iproc.c +++ b/drivers/pci/host/pcie-iproc.c @@ -111,7 +111,7 @@ static void __iomem *iproc_pcie_map_cfg_bus(struct pci_bus *bus, static struct pci_ops iproc_pcie_ops = { .map_bus = iproc_pcie_map_cfg_bus, .read = pci_generic_config_read32, - .write = pci_generic_config_write32, + .write = pci_generic_config_write, }; static void iproc_pcie_reset(struct iproc_pcie *pcie)