From patchwork Mon May 25 07:50:35 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mikko Perttunen X-Patchwork-Id: 476100 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3CFAB140129 for ; Mon, 25 May 2015 17:50:48 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750871AbbEYHur (ORCPT ); Mon, 25 May 2015 03:50:47 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:13900 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750848AbbEYHuq (ORCPT ); Mon, 25 May 2015 03:50:46 -0400 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Mon, 25 May 2015 00:50:00 -0700 Received: from HQMAIL103.nvidia.com ([172.20.12.94]) by hqnvupgp07.nvidia.com (PGP Universal service); Mon, 25 May 2015 00:48:36 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Mon, 25 May 2015 00:48:36 -0700 Received: from UKMAIL102.nvidia.com (10.26.138.15) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1044.25; Mon, 25 May 2015 07:50:45 +0000 Received: from mperttunen-lnx.Nvidia.com (10.21.25.200) by UKMAIL102.nvidia.com (10.26.138.15) with Microsoft SMTP Server (TLS) id 15.0.1044.25; Mon, 25 May 2015 07:50:41 +0000 From: Mikko Perttunen To: CC: , , , , , Mikko Perttunen Subject: [PATCH] clk: tegra: Fix zero comparison with unsigned in clk-dfll Date: Mon, 25 May 2015 10:50:35 +0300 Message-ID: <1432540235-11927-1-git-send-email-mperttunen@nvidia.com> X-Mailer: git-send-email 2.1.4 X-NVConfidentiality: public MIME-Version: 1.0 X-Originating-IP: [10.21.25.200] X-ClientProxiedBy: UKMAIL101.nvidia.com (10.26.138.13) To UKMAIL102.nvidia.com (10.26.138.15) Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The DFLL clock driver mistakenly assigned a function result value with negative error codes to an unsigned variable and then tried to check for error. Fix by assigning first to signed variable and then only to unsigned if the result was OK. Reported-by: Dan Carpenter Signed-off-by: Mikko Perttunen --- drivers/clk/tegra/clk-dfll.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/clk/tegra/clk-dfll.c b/drivers/clk/tegra/clk-dfll.c index 6ec64577..7aa6eac 100644 --- a/drivers/clk/tegra/clk-dfll.c +++ b/drivers/clk/tegra/clk-dfll.c @@ -1444,10 +1444,12 @@ static int dfll_build_i2c_lut(struct tegra_dfll *td) v_max = dev_pm_opp_get_voltage(opp); v = td->soc->min_millivolts * 1000; - td->i2c_lut[0] = find_vdd_map_entry_exact(td, v); - if (td->i2c_lut[0] < 0) + ret = find_vdd_map_entry_exact(td, v); + if (ret < 0) goto out; + td->i2c_lut[0] = ret; + for (j = 1, rate = 0; ; rate++) { opp = dev_pm_opp_find_freq_ceil(td->soc->opp_dev, &rate); if (IS_ERR(opp))