From patchwork Sun May 10 18:30:00 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Stach X-Patchwork-Id: 470521 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id EF0E1140AF3 for ; Mon, 11 May 2015 04:30:20 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751854AbbEJSaU (ORCPT ); Sun, 10 May 2015 14:30:20 -0400 Received: from ns.lynxeye.de ([87.118.118.114]:40928 "EHLO lynxeye.de" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751869AbbEJSaR (ORCPT ); Sun, 10 May 2015 14:30:17 -0400 Received: by lynxeye.de (Postfix, from userid 501) id A91F826C2001; Sun, 10 May 2015 20:30:15 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on lynxeye.de X-Spam-Level: X-Spam-Status: No, score=-2.9 required=3.0 tests=ALL_TRUSTED,BAYES_00 autolearn=ham version=3.3.1 Received: from tellur.intern.lynxeye.de (p57B5F6E7.dip0.t-ipconnect.de [87.181.246.231]) by lynxeye.de (Postfix) with ESMTPA id D7A6226C2004; Sun, 10 May 2015 20:30:11 +0200 (CEST) From: Lucas Stach To: Brian Norris , David Woodhouse , Thierry Reding , Stephen Warren Cc: Rob Herring , Pawel Moll , Mark Rutland , Alexandre Courbot , Boris BREZILLON , Ezequiel Garcia , Stefan Agner , Marcel Ziswiler , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-mtd@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [Patch v3 3/5] clk: tegra20: init NDFLASH clock to sensible rate Date: Sun, 10 May 2015 20:30:00 +0200 Message-Id: <1431282602-7137-4-git-send-email-dev@lynxeye.de> X-Mailer: git-send-email 2.1.0 In-Reply-To: <1431282602-7137-1-git-send-email-dev@lynxeye.de> References: <1431282602-7137-1-git-send-email-dev@lynxeye.de> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Set up the NAND Flash controller clock to run at 150MHz instead of the rate set by the bootloader. This is a conservative rate which also yields good performance. Signed-off-by: Lucas Stach --- drivers/clk/tegra/clk-tegra20.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index 41272dc..f20424d 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -1063,6 +1063,7 @@ static struct tegra_clk_init_table init_table[] __initdata = { {TEGRA20_CLK_DISP2, TEGRA20_CLK_PLL_P, 600000000, 0}, {TEGRA20_CLK_GR2D, TEGRA20_CLK_PLL_C, 300000000, 0}, {TEGRA20_CLK_GR3D, TEGRA20_CLK_PLL_C, 300000000, 0}, + {TEGRA20_CLK_NDFLASH, TEGRA20_CLK_PLL_P, 150000000, 0}, {TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_CLK_MAX, 0, 0}, /* This MUST be the last entry */ };