From patchwork Wed May 6 13:43:35 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 468936 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id B4B151402BF for ; Wed, 6 May 2015 23:43:44 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=GAxZqcvC; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751328AbbEFNno (ORCPT ); Wed, 6 May 2015 09:43:44 -0400 Received: from mail-pa0-f51.google.com ([209.85.220.51]:34359 "EHLO mail-pa0-f51.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751295AbbEFNnn (ORCPT ); Wed, 6 May 2015 09:43:43 -0400 Received: by pacyx8 with SMTP id yx8so9911456pac.1; Wed, 06 May 2015 06:43:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=CMsW1P4KgwCc7mBeui1zclOpuzwv+u88Sjjd1XqIS54=; b=GAxZqcvCbQqWmqagEltynGT4YMCejhv/DywNThX7EPvHkd3Eb5ckdC7FQeNwMGHKi7 8oGtbIQXIsjzhtlYACjLrxZrO9Gc9/9yAOKm7JJK3J9WfHAygKnsQ887CQpRQy3kBgpr zAYFJw1lfZVTVP3cNBoJ91Wmb8oT0cT6DOc+siRjBdaQ7kEieAuHpciuInbZFmYrVHzB T7tlCNlz6UW5uMJLUWK0jo3vSMh9fAohQlzvHhn73RXVMibjP/GuMY2nLLI9Le3+MGD0 RXSsH9cEmKpHr4f7aXr4Q+yONJ9rP0IHXweFNK0Egj9gBnbb2Wl3+h+8PHDSjrW40wIL WOvA== X-Received: by 10.70.130.43 with SMTP id ob11mr61649659pdb.35.1430919822601; Wed, 06 May 2015 06:43:42 -0700 (PDT) Received: from localhost ([216.228.120.20]) by mx.google.com with ESMTPSA id vi5sm1965033pbc.89.2015.05.06.06.43.40 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 06 May 2015 06:43:41 -0700 (PDT) From: Thierry Reding To: Benson Leung , Rhyland Klein , Peter De Schrijver Cc: Mike Turquette , Stephen Boyd , Stephen Warren , Alexandre Courbot , linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH] clk: tegra: Update struct tegra_clk_pll_params kerneldoc Date: Wed, 6 May 2015 15:43:35 +0200 Message-Id: <1430919815-22380-1-git-send-email-thierry.reding@gmail.com> X-Mailer: git-send-email 2.3.5 In-Reply-To: References: Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Benson Leung pointed out that the kerneldoc for this structure has become stale. Update the field descriptions to match the structure content. Reported-by: Benson Leung Signed-off-by: Thierry Reding Acked-by: Rhyland Klein --- drivers/clk/tegra/clk.h | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index f3782dedbdfb..c47e633616be 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -157,7 +157,7 @@ struct div_nmp { }; /** - * struct clk_pll_params - PLL parameters + * struct tegra_clk_pll_params - PLL parameters * * @input_min: Minimum input frequency * @input_max: Maximum input frequency @@ -168,12 +168,22 @@ struct div_nmp { * @base_reg: PLL base reg offset * @misc_reg: PLL misc reg offset * @lock_reg: PLL lock reg offset - * @lock_bit_idx: Bit index for PLL lock status + * @lock_mask: Bitmask for PLL lock status * @lock_enable_bit_idx: Bit index to enable PLL lock + * @iddq_reg: PLL IDDQ register offset + * @iddq_bit_idx: Bit index to enable PLL IDDQ + * @aux_reg: AUX register offset + * @dyn_ramp_reg: Dynamic ramp control register offset + * @ext_misc_reg: Miscellaneous control register offsets + * @pmc_divnm_reg: n, m divider PMC override register offset (PLLM) + * @pmc_divp_reg: p divider PMC override register offset (PLLM) + * @flags: PLL flags + * @stepa_shift: Dynamic ramp step A field shift + * @stepb_shift: Dynamic ramp step B field shift * @lock_delay: Delay in us if PLL lock is not used + * @div_nmp: offsets and widths on n, m and p fields * @freq_table: array of frequencies supported by PLL * @fixed_rate: PLL rate if it is fixed - * @flags: PLL flags * * Flags: * TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for