Message ID | 1430919815-22380-1-git-send-email-thierry.reding@gmail.com |
---|---|
State | Superseded |
Headers | show |
On 5/6/2015 9:43 AM, Thierry Reding wrote: > From: Thierry Reding <treding@nvidia.com> > > Benson Leung pointed out that the kerneldoc for this structure has > become stale. Update the field descriptions to match the structure > content. > > Reported-by: Benson Leung <bleung@chromium.org> > Signed-off-by: Thierry Reding <treding@nvidia.com> > --- > drivers/clk/tegra/clk.h | 16 +++++++++++++--- > 1 file changed, 13 insertions(+), 3 deletions(-) > > diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h > index f3782dedbdfb..c47e633616be 100644 > --- a/drivers/clk/tegra/clk.h > +++ b/drivers/clk/tegra/clk.h > @@ -157,7 +157,7 @@ struct div_nmp { > }; > > /** > - * struct clk_pll_params - PLL parameters > + * struct tegra_clk_pll_params - PLL parameters > * > * @input_min: Minimum input frequency > * @input_max: Maximum input frequency > @@ -168,12 +168,22 @@ struct div_nmp { > * @base_reg: PLL base reg offset > * @misc_reg: PLL misc reg offset > * @lock_reg: PLL lock reg offset > - * @lock_bit_idx: Bit index for PLL lock status > + * @lock_mask: Bitmask for PLL lock status > * @lock_enable_bit_idx: Bit index to enable PLL lock > + * @iddq_reg: PLL IDDQ register offset > + * @iddq_bit_idx: Bit index to enable PLL IDDQ > + * @aux_reg: AUX register offset > + * @dyn_ramp_reg: Dynamic ramp control register offset > + * @ext_misc_reg: Miscellaneous control register offsets > + * @pmc_divnm_reg: n, m divider PMC override register offset (PLLM) > + * @pmc_divp_reg: p divider PMC override register offset (PLLM) > + * @flags: PLL flags > + * @stepa_shift: Dynamic ramp step A field shift > + * @stepb_shift: Dynamic ramp step B field shift > * @lock_delay: Delay in us if PLL lock is not used > + * @div_nmp: offsets and widths on n, m and p fields > * @freq_table: array of frequencies supported by PLL > * @fixed_rate: PLL rate if it is fixed > - * @flags: PLL flags > * > * Flags: > * TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for > Acked-by: Rhyland Klein <rklein@nvidia.com> -rhyland
On Wed, May 6, 2015 at 6:43 AM, Thierry Reding <thierry.reding@gmail.com> wrote: > From: Thierry Reding <treding@nvidia.com> > > Benson Leung pointed out that the kerneldoc for this structure has > become stale. Update the field descriptions to match the structure > content. > > Reported-by: Benson Leung <bleung@chromium.org> > Signed-off-by: Thierry Reding <treding@nvidia.com> > --- > drivers/clk/tegra/clk.h | 16 +++++++++++++--- > 1 file changed, 13 insertions(+), 3 deletions(-) > > diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h > index f3782dedbdfb..c47e633616be 100644 > --- a/drivers/clk/tegra/clk.h > +++ b/drivers/clk/tegra/clk.h > @@ -157,7 +157,7 @@ struct div_nmp { > }; > > /** > - * struct clk_pll_params - PLL parameters > + * struct tegra_clk_pll_params - PLL parameters > * > * @input_min: Minimum input frequency > * @input_max: Maximum input frequency > @@ -168,12 +168,22 @@ struct div_nmp { > * @base_reg: PLL base reg offset > * @misc_reg: PLL misc reg offset > * @lock_reg: PLL lock reg offset > - * @lock_bit_idx: Bit index for PLL lock status > + * @lock_mask: Bitmask for PLL lock status > * @lock_enable_bit_idx: Bit index to enable PLL lock > + * @iddq_reg: PLL IDDQ register offset > + * @iddq_bit_idx: Bit index to enable PLL IDDQ > + * @aux_reg: AUX register offset > + * @dyn_ramp_reg: Dynamic ramp control register offset > + * @ext_misc_reg: Miscellaneous control register offsets > + * @pmc_divnm_reg: n, m divider PMC override register offset (PLLM) > + * @pmc_divp_reg: p divider PMC override register offset (PLLM) > + * @flags: PLL flags > + * @stepa_shift: Dynamic ramp step A field shift > + * @stepb_shift: Dynamic ramp step B field shift > * @lock_delay: Delay in us if PLL lock is not used Missed a couple - @max_p: @pdiv_tohw: Thanks!
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index f3782dedbdfb..c47e633616be 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -157,7 +157,7 @@ struct div_nmp { }; /** - * struct clk_pll_params - PLL parameters + * struct tegra_clk_pll_params - PLL parameters * * @input_min: Minimum input frequency * @input_max: Maximum input frequency @@ -168,12 +168,22 @@ struct div_nmp { * @base_reg: PLL base reg offset * @misc_reg: PLL misc reg offset * @lock_reg: PLL lock reg offset - * @lock_bit_idx: Bit index for PLL lock status + * @lock_mask: Bitmask for PLL lock status * @lock_enable_bit_idx: Bit index to enable PLL lock + * @iddq_reg: PLL IDDQ register offset + * @iddq_bit_idx: Bit index to enable PLL IDDQ + * @aux_reg: AUX register offset + * @dyn_ramp_reg: Dynamic ramp control register offset + * @ext_misc_reg: Miscellaneous control register offsets + * @pmc_divnm_reg: n, m divider PMC override register offset (PLLM) + * @pmc_divp_reg: p divider PMC override register offset (PLLM) + * @flags: PLL flags + * @stepa_shift: Dynamic ramp step A field shift + * @stepb_shift: Dynamic ramp step B field shift * @lock_delay: Delay in us if PLL lock is not used + * @div_nmp: offsets and widths on n, m and p fields * @freq_table: array of frequencies supported by PLL * @fixed_rate: PLL rate if it is fixed - * @flags: PLL flags * * Flags: * TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for