From patchwork Wed Mar 25 06:48:35 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Zhang X-Patchwork-Id: 454235 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 8FEFF1400DD for ; Wed, 25 Mar 2015 17:48:57 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751029AbbCYGsz (ORCPT ); Wed, 25 Mar 2015 02:48:55 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:4018 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750710AbbCYGsz (ORCPT ); Wed, 25 Mar 2015 02:48:55 -0400 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Tue, 24 Mar 2015 23:49:35 -0700 Received: from hqemhub02.nvidia.com ([172.20.12.94]) by hqnvupgp07.nvidia.com (PGP Universal service); Tue, 24 Mar 2015 23:46:49 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Tue, 24 Mar 2015 23:46:49 -0700 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by hqemhub02.nvidia.com (172.20.150.31) with Microsoft SMTP Server id 8.3.342.0; Tue, 24 Mar 2015 23:48:54 -0700 Received: from markz-hp6200.nvidia.com (Not Verified[10.19.224.127]) by hqnvemgw02.nvidia.com with MailMarshal (v7,1,2,5326) id ; Tue, 24 Mar 2015 23:48:53 -0700 From: Mark Zhang To: thierry.reding@gmail.com CC: linux-tegra@vger.kernel.org, Mark Zhang Subject: [PATCH] drm/panel: sharp: lq101r1sx01: Send cmds to panel from link2 Date: Wed, 25 Mar 2015 14:48:35 +0800 Message-ID: <1427266115-31644-1-git-send-email-markz@nvidia.com> X-Mailer: git-send-email 2.1.4 X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Sharp lq101r1sx01 panel works as left-right gang mode. So link2 should send cmds like "exit sleep mode", "set display on" to panel as well. Signed-off-by: Mark Zhang --- drivers/gpu/drm/panel/panel-sharp-lq101r1sx01.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/gpu/drm/panel/panel-sharp-lq101r1sx01.c b/drivers/gpu/drm/panel/panel-sharp-lq101r1sx01.c index 3cce3ca19601..e7c094dbf2e4 100644 --- a/drivers/gpu/drm/panel/panel-sharp-lq101r1sx01.c +++ b/drivers/gpu/drm/panel/panel-sharp-lq101r1sx01.c @@ -193,6 +193,12 @@ static int sharp_panel_prepare(struct drm_panel *panel) dev_err(panel->dev, "failed to exit sleep mode: %d\n", err); goto poweroff; } + err = mipi_dsi_dcs_exit_sleep_mode(sharp->link2); + if (err < 0) { + dev_err(panel->dev, "link2: failed to exit sleep mode: %d\n", + err); + goto poweroff; + } /* * The MIPI DCS specification mandates this delay only between the @@ -222,6 +228,12 @@ static int sharp_panel_prepare(struct drm_panel *panel) dev_err(panel->dev, "failed to set pixel format: %d\n", err); goto poweroff; } + err = mipi_dsi_dcs_set_pixel_format(sharp->link2, format); + if (err < 0) { + dev_err(panel->dev, "link2: failed to set pixel format: %d\n", + err); + goto poweroff; + } /* * TODO: The device supports both left-right and even-odd split @@ -243,6 +255,12 @@ static int sharp_panel_prepare(struct drm_panel *panel) dev_err(panel->dev, "failed to set display on: %d\n", err); goto poweroff; } + err = mipi_dsi_dcs_set_display_on(sharp->link2); + if (err < 0) { + dev_err(panel->dev, "link2: failed to set display on: %d\n", + err); + goto poweroff; + } sharp->prepared = true;