From patchwork Tue Mar 12 23:40:50 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: achew@nvidia.com X-Patchwork-Id: 227128 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 6CFA82C0298 for ; Wed, 13 Mar 2013 10:41:16 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932606Ab3CLXlP (ORCPT ); Tue, 12 Mar 2013 19:41:15 -0400 Received: from hqemgate04.nvidia.com ([216.228.121.35]:4976 "EHLO hqemgate04.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755329Ab3CLXlO (ORCPT ); Tue, 12 Mar 2013 19:41:14 -0400 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate04.nvidia.com id ; Tue, 12 Mar 2013 16:41:10 -0700 Received: from hqemhub02.nvidia.com ([172.17.108.22]) by hqnvupgp07.nvidia.com (PGP Universal service); Tue, 12 Mar 2013 16:41:13 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Tue, 12 Mar 2013 16:41:13 -0700 Received: from achew-linux64.nvidia.com (172.20.144.16) by hqemhub02.nvidia.com (172.20.150.31) with Microsoft SMTP Server (TLS) id 8.3.298.1; Tue, 12 Mar 2013 16:41:13 -0700 From: Andrew Chew To: , CC: , Subject: [PATCH 1/2 v4] ARM: tegra: add PWM nodes to Tegra114 DT Date: Tue, 12 Mar 2013 16:40:50 -0700 Message-ID: <1363131651-13734-1-git-send-email-achew@nvidia.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org This patch adds a device tree node for the four PWM controllers present on Tegra114. Signed-off-by: Andrew Chew --- Change the register base length to 0x100, per TRM. arch/arm/boot/dts/tegra114.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index 1dfaf28..3b20d14 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -92,6 +92,14 @@ status = "disabled"; }; + pwm: pwm { + compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm"; + reg = <0x7000a000 0x100>; + #pwm-cells = <2>; + clocks = <&tegra_car 17>; + status = "disabled"; + }; + rtc { compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc"; reg = <0x7000e000 0x100>;