Message ID | 1363131651-13734-1-git-send-email-achew@nvidia.com |
---|---|
State | Accepted, archived |
Headers | show |
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index 1dfaf28..3b20d14 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -92,6 +92,14 @@ status = "disabled"; }; + pwm: pwm { + compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm"; + reg = <0x7000a000 0x100>; + #pwm-cells = <2>; + clocks = <&tegra_car 17>; + status = "disabled"; + }; + rtc { compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc"; reg = <0x7000e000 0x100>;
This patch adds a device tree node for the four PWM controllers present on Tegra114. Signed-off-by: Andrew Chew <achew@nvidia.com> --- Change the register base length to 0x100, per TRM. arch/arm/boot/dts/tegra114.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+)