From patchwork Wed Feb 6 18:34:26 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hiroshi Doyu X-Patchwork-Id: 218712 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 9B5B22C02EA for ; Thu, 7 Feb 2013 05:34:54 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755389Ab3BFSex (ORCPT ); Wed, 6 Feb 2013 13:34:53 -0500 Received: from hqemgate04.nvidia.com ([216.228.121.35]:5176 "EHLO hqemgate04.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755382Ab3BFSew (ORCPT ); Wed, 6 Feb 2013 13:34:52 -0500 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate04.nvidia.com id ; Wed, 06 Feb 2013 10:34:33 -0800 Received: from hqemhub01.nvidia.com ([172.17.108.22]) by hqnvupgp08.nvidia.com (PGP Universal service); Wed, 06 Feb 2013 10:31:39 -0800 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Wed, 06 Feb 2013 10:31:39 -0800 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by hqemhub01.nvidia.com (172.20.150.30) with Microsoft SMTP Server id 8.3.297.1; Wed, 6 Feb 2013 10:34:43 -0800 Received: from daphne.nvidia.com (Not Verified[172.16.212.96]) by hqnvemgw01.nvidia.com with MailMarshal (v6,7,2,8378) id ; Wed, 06 Feb 2013 10:36:02 -0800 Received: from oreo.Nvidia.com (dhcp-10-21-25-186.nvidia.com [10.21.25.186]) by daphne.nvidia.com (8.13.8+Sun/8.8.8) with ESMTP id r16IYfQc011742; Wed, 6 Feb 2013 10:34:42 -0800 (PST) From: Hiroshi Doyu To: CC: , , Hiroshi Doyu , Subject: [PATCH 1/1] memory: tegra_ahb_enable_smmu() depends on TEGRA_IOMMU_SMMU Date: Wed, 6 Feb 2013 20:34:26 +0200 Message-ID: <1360175666-8377-1-git-send-email-hdoyu@nvidia.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org New SoC, Tegra114 also uses SMMU. Change tegra_ahb_enable_smmu()'s dependency from ARCH_TEGRA_3x_SOC to TEGRA_IOMMU_SMMU. No need to edit whenever a new Tegra SoC comes. The following combination caused build error, which this patch fixes. CONFIG_ARCH_TEGRA_2x_SOC=y \# CONFIG_ARCH_TEGRA_3x_SOC is not set CONFIG_ARCH_TEGRA_114_SOC=y drivers/iommu/tegra-smmu.c:485: undefined reference to 'tegra_ahb_enable_smmu' Signed-off-by: Hiroshi Doyu Tested-by: Stephen Warren --- drivers/amba/tegra-ahb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/amba/tegra-ahb.c b/drivers/amba/tegra-ahb.c index ab92785..093c435 100644 --- a/drivers/amba/tegra-ahb.c +++ b/drivers/amba/tegra-ahb.c @@ -130,7 +130,7 @@ static inline void gizmo_writel(struct tegra_ahb *ahb, u32 value, u32 offset) writel(value, ahb->regs + offset); } -#ifdef CONFIG_ARCH_TEGRA_3x_SOC +#ifdef CONFIG_TEGRA_IOMMU_SMMU static int tegra_ahb_match_by_smmu(struct device *dev, void *data) { struct tegra_ahb *ahb = dev_get_drvdata(dev);