From patchwork Tue Oct 16 10:08:36 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sivaram Nair X-Patchwork-Id: 191764 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id B62A42C0084 for ; Tue, 16 Oct 2012 21:10:27 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752105Ab2JPKK0 (ORCPT ); Tue, 16 Oct 2012 06:10:26 -0400 Received: from hqemgate04.nvidia.com ([216.228.121.35]:3618 "EHLO hqemgate04.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752567Ab2JPKKZ (ORCPT ); Tue, 16 Oct 2012 06:10:25 -0400 Received: from hqnvupgp06.nvidia.com (Not Verified[216.228.121.13]) by hqemgate04.nvidia.com id ; Tue, 16 Oct 2012 03:09:43 -0700 Received: from hqemhub02.nvidia.com ([172.17.108.22]) by hqnvupgp06.nvidia.com (PGP Universal service); Tue, 16 Oct 2012 03:10:16 -0700 X-PGP-Universal: processed; by hqnvupgp06.nvidia.com on Tue, 16 Oct 2012 03:10:16 -0700 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by hqemhub02.nvidia.com (172.20.150.31) with Microsoft SMTP Server id 8.3.264.0; Tue, 16 Oct 2012 03:10:15 -0700 Received: from daphne.nvidia.com (Not Verified[172.16.212.96]) by hqnvemgw01.nvidia.com with MailMarshal (v6,7,2,8378) id ; Tue, 16 Oct 2012 03:10:16 -0700 Received: from localhost.localdomain (dhcp-10-21-25-217.nvidia.com [10.21.25.217]) by daphne.nvidia.com (8.13.8+Sun/8.8.8) with ESMTP id q9GAA6sW014247; Tue, 16 Oct 2012 03:10:14 -0700 (PDT) From: Sivaram Nair To: , , , CC: , Subject: [PATCH 2/2] ARM: tegra: add tegra_timer clock Date: Tue, 16 Oct 2012 13:08:36 +0300 Message-ID: <1350382116-18024-3-git-send-email-sivaramn@nvidia.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1350382116-18024-1-git-send-email-sivaramn@nvidia.com> References: <1350382116-18024-1-git-send-email-sivaramn@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Sivaram Nair This undoes commit 20f4665831cec65d6e5d33587bba28ffa536b91d by bringing back the tegra_timer clock. tegra_timer is indeed a clock (hidden by the PERIPH_CLK macro) which should be added to the tegra_list_clks. The above commit caused tegra_init_timer() failing to get the clk reference. Signed-off-by: Sivaram Nair --- arch/arm/mach-tegra/tegra20_clocks_data.c | 1 + arch/arm/mach-tegra/tegra30_clocks_data.c | 1 + 2 files changed, 2 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-tegra/tegra20_clocks_data.c b/arch/arm/mach-tegra/tegra20_clocks_data.c index cc9b5fd..8d398a3 100644 --- a/arch/arm/mach-tegra/tegra20_clocks_data.c +++ b/arch/arm/mach-tegra/tegra20_clocks_data.c @@ -953,6 +953,7 @@ PERIPH_CLK(pcie_xclk, NULL, "pcie_xclk", 74, 0, 26000000, mux_clk_m, static struct clk *tegra_list_clks[] = { &tegra_apbdma, &tegra_rtc, + &tegra_timer, &tegra_i2s1, &tegra_i2s2, &tegra_spdif_out, diff --git a/arch/arm/mach-tegra/tegra30_clocks_data.c b/arch/arm/mach-tegra/tegra30_clocks_data.c index d92cb55..3d2e553 100644 --- a/arch/arm/mach-tegra/tegra30_clocks_data.c +++ b/arch/arm/mach-tegra/tegra30_clocks_data.c @@ -1143,6 +1143,7 @@ struct clk *tegra_list_clks[] = { &tegra_apbdma, &tegra_rtc, &tegra_kbc, + &tegra_timer, &tegra_kfuse, &tegra_fuse, &tegra_fuse_burn,