From patchwork Thu Sep 5 10:45:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 1158345 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="h7w1/lHC"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 46PHRM3FcCz9s7T for ; Thu, 5 Sep 2019 20:46:07 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732028AbfIEKqH (ORCPT ); Thu, 5 Sep 2019 06:46:07 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:9996 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727900AbfIEKqG (ORCPT ); Thu, 5 Sep 2019 06:46:06 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 05 Sep 2019 03:46:08 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Thu, 05 Sep 2019 03:46:06 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Thu, 05 Sep 2019 03:46:06 -0700 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 5 Sep 2019 10:46:01 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Thu, 5 Sep 2019 10:46:01 +0000 Received: from vidyas-desktop.nvidia.com (Not Verified[10.24.37.38]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Thu, 05 Sep 2019 03:46:00 -0700 From: Vidya Sagar To: , , , , , CC: , , , , , , , , , , , , Subject: [PATCH V4 0/6] PCI: tegra: Enable PCIe C5 controller of Tegra194 in p2972-0000 platform Date: Thu, 5 Sep 2019 16:15:47 +0530 Message-ID: <20190905104553.2884-1-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1567680368; bh=YC2A14ccqRxtxcn75mXI1dozxpBOosnoSmsvsyfnYmk=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: X-NVConfidentiality:MIME-Version:Content-Type; b=h7w1/lHCXzCaLLHTK+O6GLMLqzoa0L15XNlxklPoeAIAYlTPo9qnb/TgA8+RA6/NK LwSSZLM2y+oVs2bqt/8rIsiBUuUJbb+YoQHJNEkRTMvI6jvX9M6+LGLXg/H+N8s1p1 kg/uW2AvO2Q/c3BW9k/cRB+IzuptrKaSxvtLoA2LvKzh4B8gqeTozPht2ap29Zgz35 PYtYAAX+yOqcHKI5WXHr90tO30NgWCvbVZus/+PHd6KZwyz3Ye2Ml3VjFDD6h99R6n G2g2gMD9fNjx27Wce/pUOCbhWV2SManYwaj5TScqus+Uw3v9IyIbmI9aJte9qfA3eu vUkmUjfg7BEOQ== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org This patch series enables Tegra194's C5 controller which owns x16 slot in p2972-0000 platform. C5 controller's PERST# and CLKREQ# are not configured as output and bi-directional signals by default and hence they need to be configured explicitly. Also, x16 slot's 3.3V and 12V supplies are controlled through GPIOs and hence they need to be enabled through regulator framework. This patch series adds required infrastructural support to address both the aforementioned requirements. Testing done on p2972-0000 platform - Able to enumerate devices connected to x16 slot (owned by C5 controller) - Enumerated device's functionality verified - Suspend-Resume sequence is verified with device connected to x16 slot V4: * Rebased (Patch-4/6 particularly) on top of Lorenzo's pci/tegra branch V3: * Addressed some more review comments from Andrew Murray and Thierry Reding V2: * Changed the order of patches in the series for easy merging * Addressed review comments from Thierry Reding and Andrew Murray Vidya Sagar (6): dt-bindings: PCI: tegra: Add sideband pins configuration entries dt-bindings: PCI: tegra: Add PCIe slot supplies regulator entries PCI: tegra: Add support to configure sideband pins PCI: tegra: Add support to enable slot regulators arm64: tegra: Add configuration for PCIe C5 sideband signals arm64: tegra: Add PCIe slot supply information in p2972-0000 platform .../bindings/pci/nvidia,tegra194-pcie.txt | 16 ++++ .../arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 24 +++++ .../boot/dts/nvidia/tegra194-p2972-0000.dts | 4 +- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 38 +++++++- drivers/pci/controller/dwc/pcie-tegra194.c | 94 ++++++++++++++++++- 5 files changed, 172 insertions(+), 4 deletions(-)