From patchwork Thu Oct 12 18:50:05 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 825018 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yCg1X2rNzz9sNV for ; Fri, 13 Oct 2017 05:51:44 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751937AbdJLSvn (ORCPT ); Thu, 12 Oct 2017 14:51:43 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:10431 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751348AbdJLSvm (ORCPT ); Thu, 12 Oct 2017 14:51:42 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Thu, 12 Oct 2017 11:51:11 -0700 Received: from HQMAIL108.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 12 Oct 2017 11:51:21 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 12 Oct 2017 11:51:21 -0700 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Thu, 12 Oct 2017 18:50:17 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server id 15.0.1293.2 via Frontend Transport; Thu, 12 Oct 2017 18:50:17 +0000 Received: from vidyas-desktop.nvidia.com (Not Verified[10.24.36.185]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Thu, 12 Oct 2017 11:50:17 -0700 From: Vidya Sagar To: , CC: , , , Vidya Sagar Subject: [PATCH 0/6] Tegra PCIe end point config space map code refactoring Date: Fri, 13 Oct 2017 00:20:05 +0530 Message-ID: <1507834211-24922-1-git-send-email-vidyas@nvidia.com> X-Mailer: git-send-email 2.7.4 X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org PCIe host controller in Tegra SoCs has 1GB of aperture available for mapping end points config space, IO and BARs. In that, currently 256MB is being reserved for mapping end points configuration space which leaves less memory space available for mapping end points BARs on some of the platforms. This patch series attempts to use only 4K space from 1GB aperture to access end points configuration space. Currently, this change benefits T20 and future chips in saving (i.e. repurposed to use for BAR mapping) physical space as well as kernel virtual mapping space, it saves only kernel virtual address space in T30, T124, T132 and T210. Testing Done on T210: Enumeration is and basic functionality of immediate devices Enumeration of devices behind a PCIe switch Complete 4K configuration space access Vidya Sagar (6): PCI: tegra: refactor config space mapping code ARM: tegra: limit PCIe config space mapping to 4K for T20 ARM: tegra: limit PCIe config space mapping to 4K for T30 ARM: tegra: limit PCIe config space mapping to 4K for T124 ARM64: tegra: limit PCIe config space mapping to 4K for T132 ARM64: tegra: limit PCIe config space mapping to 4K for T210 arch/arm/boot/dts/tegra124.dtsi | 2 +- arch/arm/boot/dts/tegra20.dtsi | 8 +-- arch/arm/boot/dts/tegra30.dtsi | 2 +- arch/arm64/boot/dts/nvidia/tegra132.dtsi | 2 +- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 2 +- drivers/pci/host/pci-tegra.c | 85 +++++++++----------------------- 6 files changed, 31 insertions(+), 70 deletions(-) Reviewed-by: Manikanta Maddireddy Tested-by: Manikanta Maddireddy