Message ID | 56550a6c9ba94c170d32b1f7c076b6faee42ae9f.1729037302.git.unicorn_wang@outlook.com |
---|---|
State | Superseded |
Headers | show
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Tue, 15 Oct 2024 17:20:47 -0700 (PDT) Received: from localhost.localdomain ([122.8.183.87]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-288dab8a172sm623857fac.6.2024.10.15.17.20.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Oct 2024 17:20:47 -0700 (PDT) From: Chen Wang <unicornxw@gmail.com> To: ukleinek@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, unicorn_wang@outlook.com, inochiama@outlook.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, linux-riscv@lists.infradead.org, chao.wei@sophgo.com, haijiao.liu@sophgo.com, xiaoguang.xing@sophgo.com, chunzhi.lin@sophgo.com Subject: [PATCH v4 3/3] riscv: sophgo: dts: add pwm controller for SG2042 SoC Date: Wed, 16 Oct 2024 08:20:40 +0800 Message-Id: <56550a6c9ba94c170d32b1f7c076b6faee42ae9f.1729037302.git.unicorn_wang@outlook.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <cover.1729037302.git.unicorn_wang@outlook.com> References: <cover.1729037302.git.unicorn_wang@outlook.com> Precedence: bulk X-Mailing-List: linux-pwm@vger.kernel.org List-Id: <linux-pwm.vger.kernel.org> List-Subscribe: <mailto:linux-pwm+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:linux-pwm+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit |
Series |
pwm: Add pwm driver for Sophgo SG2042
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diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi index 4e5fa6591623..048792b30617 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi @@ -165,6 +165,14 @@ port2a: gpio-controller@0 { }; }; + pwm: pwm@703000c000 { + compatible = "sophgo,sg2042-pwm"; + reg = <0x70 0x3000c000 0x0 0x20>; + #pwm-cells = <2>; + clocks = <&clkgen GATE_CLK_APB_PWM>; + clock-names = "apb"; + }; + pllclk: clock-controller@70300100c0 { compatible = "sophgo,sg2042-pll"; reg = <0x70 0x300100c0 0x0 0x40>;