Message ID | 20240520184227.120956-4-privatesub2@gmail.com |
---|---|
State | Deferred |
Headers | show
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Mon, 20 May 2024 11:43:13 -0700 (PDT) Received: from localhost.localdomain ([188.162.49.81]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-521f38d335csm4368967e87.125.2024.05.20.11.43.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 May 2024 11:43:13 -0700 (PDT) From: Aleksandr Shubin <privatesub2@gmail.com> To: linux-kernel@vger.kernel.org Cc: Aleksandr Shubin <privatesub2@gmail.com>, =?utf-8?q?Uwe_Kleine-K=C3=B6ni?= =?utf-8?q?g?= <ukleinek@kernel.org>, Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley <conor+dt@kernel.org>, Chen-Yu Tsai <wens@csie.org>, Jernej Skrabec <jernej.skrabec@gmail.com>, Samuel Holland <samuel@sholland.org>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Philipp Zabel <p.zabel@pengutronix.de>, John Watts <contact@jookia.org>, Marc Kleine-Budde <mkl@pengutronix.de>, Maksim Kiselev <bigunclemax@gmail.com>, Cheo Fusi <fusibrandon13@gmail.com>, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-riscv@lists.infradead.org Subject: [PATCH v9 3/3] riscv: dts: allwinner: d1: Add pwm node Date: Mon, 20 May 2024 21:42:21 +0300 Message-Id: <20240520184227.120956-4-privatesub2@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240520184227.120956-1-privatesub2@gmail.com> References: <20240520184227.120956-1-privatesub2@gmail.com> Precedence: bulk X-Mailing-List: linux-pwm@vger.kernel.org List-Id: <linux-pwm.vger.kernel.org> List-Subscribe: <mailto:linux-pwm+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:linux-pwm+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit |
Series | Add support for Allwinner PWM on D1/T113s/R329 SoCs | expand |
diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi index 5a9d7f5a75b4..22821b21b9a2 100644 --- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi @@ -145,6 +145,18 @@ uart3_pb_pins: uart3-pb-pins { }; }; + pwm: pwm@2000c00 { + compatible = "allwinner,sun20i-d1-pwm"; + reg = <0x02000c00 0x400>; + clocks = <&ccu CLK_BUS_PWM>, + <&dcxo>, + <&ccu CLK_APB0>; + clock-names = "bus", "hosc", "apb"; + resets = <&ccu RST_BUS_PWM>; + status = "disabled"; + #pwm-cells = <0x3>; + }; + ccu: clock-controller@2001000 { compatible = "allwinner,sun20i-d1-ccu"; reg = <0x2001000 0x1000>;
D1 and T113s contain a pwm controller with 8 channels. This controller is supported by the sun20i-pwm driver. Add a device tree node for it. Signed-off-by: Aleksandr Shubin <privatesub2@gmail.com> --- arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+)