From patchwork Tue Sep 27 16:24:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 1683401 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=WZYd2Zhw; dkim-atps=neutral Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4McQ1g4RKhz1yq3 for ; Wed, 28 Sep 2022 02:24:23 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233004AbiI0QYV (ORCPT ); Tue, 27 Sep 2022 12:24:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38766 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229691AbiI0QYK (ORCPT ); Tue, 27 Sep 2022 12:24:10 -0400 Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1874315EF98; Tue, 27 Sep 2022 09:24:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1664295850; x=1695831850; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=A9XwjcYhm5i/e8vIjenDrCHIcT6qFMQ1yXOriuZ1ixc=; b=WZYd2ZhwG7glfegqrVJOPGOJhaefmKU6cl3/AT34/lCjL0q3+V/pojAn RCdXN6JopcneKQZ/sBTuYHarCQIUOxg2F/Whym1rJ2dGYseAZMCm8zdcx TnKOqI0/bhBkYcFjX6Xra9BnRwmlFLZOtw5uZgiQ+dPr2H2jvcxujxFZq fN6hsqiAgWyaHY0Xu6531hGqfqrEVUce5Pbj1sNWzGm7lz6ZubZb2/1WI iHyLUQNX2MW1Q5ORkhtBUVYsovaGQbys3eA3aDyLWxtYA0t29jPbWL00C iid9bEpmAzEBzK19ccacGL+e6BlGG5Xkd/nb29R3tp1C9EjM4zih/LIBp Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10483"; a="327719524" X-IronPort-AV: E=Sophos;i="5.93,349,1654585200"; d="scan'208";a="327719524" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Sep 2022 09:24:09 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10483"; a="763935923" X-IronPort-AV: E=Sophos;i="5.93,349,1654585200"; d="scan'208";a="763935923" Received: from black.fi.intel.com ([10.237.72.28]) by fmsmga001.fm.intel.com with ESMTP; 27 Sep 2022 09:24:08 -0700 Received: by black.fi.intel.com (Postfix, from userid 1003) id A41C850D; Tue, 27 Sep 2022 19:24:23 +0300 (EEST) From: Andy Shevchenko To: Hans de Goede , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Andy Shevchenko , linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Thierry Reding Subject: [PATCH v4 6/7] pwm: lpss: Make use of bits.h macros for all masks Date: Tue, 27 Sep 2022 19:24:20 +0300 Message-Id: <20220927162421.11052-7-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220927162421.11052-1-andriy.shevchenko@linux.intel.com> References: <20220927162421.11052-1-andriy.shevchenko@linux.intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org Make use of the GENMASK() (far less error-prone, far more concise). Signed-off-by: Andy Shevchenko Reviewed-by: Hans de Goede Acked-by: Uwe Kleine-König --- drivers/pwm/pwm-lpss.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pwm/pwm-lpss.c b/drivers/pwm/pwm-lpss.c index a20915459809..accdef5dd58e 100644 --- a/drivers/pwm/pwm-lpss.c +++ b/drivers/pwm/pwm-lpss.c @@ -10,6 +10,7 @@ * Author: Alan Cox */ +#include #include #include #include @@ -26,7 +27,7 @@ #define PWM_ENABLE BIT(31) #define PWM_SW_UPDATE BIT(30) #define PWM_BASE_UNIT_SHIFT 8 -#define PWM_ON_TIME_DIV_MASK 0x000000ff +#define PWM_ON_TIME_DIV_MASK GENMASK(7, 0) /* Size of each PWM register space if multiple */ #define PWM_SIZE 0x400