From patchwork Wed Mar 2 15:32:03 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lee Jones X-Patchwork-Id: 591023 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 63C8E140079 for ; Thu, 3 Mar 2016 02:44:59 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b=gIvEsKI4; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755362AbcCBPom (ORCPT ); Wed, 2 Mar 2016 10:44:42 -0500 Received: from mail-wm0-f50.google.com ([74.125.82.50]:32884 "EHLO mail-wm0-f50.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750977AbcCBPeU (ORCPT ); Wed, 2 Mar 2016 10:34:20 -0500 Received: by mail-wm0-f50.google.com with SMTP id l68so85655815wml.0 for ; Wed, 02 Mar 2016 07:34:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=IFESZwlOLqSbn4OrxWQ3nTTQplgmzwcWRWqqbuq2VBo=; b=gIvEsKI4EA+J8oMAI5/3QK8+JmlXhfpPkDB/jQu/fiuGli0av/at0jcyS8DWrbBc6N 7/Qn3ctsq7EKXvmb08pfC1kgIILkWPaW3NMPWdcHjj0X2mt5q6n+5RB5dwb2si1qYg8w S65k3lFlj/S92BACsEbZrIJ6k5TEc/cqNAUHA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=IFESZwlOLqSbn4OrxWQ3nTTQplgmzwcWRWqqbuq2VBo=; b=QarvJX+YdTfQiS7LKffybcnyeDxBca+w5Q45NwGwhM5BAbwU4BUKc1fP9EYJhIwsLX dTslXIc1YQOs+DbqR5EqfMkVUbMr0/B+xfMMdSlsNgR7Ovx9HpyVPg1ruJ3i5j2L2S7E twbUD7ghsCiQOHZVI73ncFjsgOhhxVQnhuCW+VFvuPMXugedR98feUHcqLLGzuWAkKVY L7xn04DkZ33ik2mK6kPDrFfgAtLhhZtPk1rPGRprKie18VdkPTcImOuIrvKbQe4vPvbM Eo7Rp3BHaBn0+NTTwHm4lYc9QbGI3C+5m+QvziHdqopjr+jAontfRbERqDPN/6YvhSmB Gb8g== X-Gm-Message-State: AD7BkJJnwfete/2K113tgNsrTWScXx9AF0egEMEs5smM5p4xu9tp+JNwVTqsFwjNJFPv930Y X-Received: by 10.194.175.33 with SMTP id bx1mr27053284wjc.104.1456932858981; Wed, 02 Mar 2016 07:34:18 -0800 (PST) Received: from localhost.localdomain (host81-154-142-245.range81-154.btcentralplus.com. [81.154.142.245]) by smtp.gmail.com with ESMTPSA id da6sm26941407wjb.24.2016.03.02.07.34.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 02 Mar 2016 07:34:18 -0800 (PST) From: Lee Jones To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: kernel@stlinux.com, maxime.coquelin@st.com, thierry.reding@gmail.com, linux-pwm@vger.kernel.org, ajitpal.singh@st.com, Lee Jones Subject: [RESEND 05/11] pwm: sti: Supply PWM Capture register addresses and bit locations Date: Wed, 2 Mar 2016 15:32:03 +0000 Message-Id: <1456932729-9667-6-git-send-email-lee.jones@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1456932729-9667-1-git-send-email-lee.jones@linaro.org> References: <1456932729-9667-1-git-send-email-lee.jones@linaro.org> Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org Signed-off-by: Lee Jones --- drivers/pwm/pwm-sti.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/drivers/pwm/pwm-sti.c b/drivers/pwm/pwm-sti.c index aa217e2..2336bac 100644 --- a/drivers/pwm/pwm-sti.c +++ b/drivers/pwm/pwm-sti.c @@ -22,26 +22,48 @@ #include #define PWM_OUT_VAL(x) (0x00 + (4 * (x))) /* Channel's Duty Cycle register */ +#define PWM_CPT_VAL(x) (0x10 + (4 * (x))) /* Capture value */ +#define PWM_CPT_EDGE(x) (0x30 + (4 * (x))) /* Edge to capture on */ #define STI_PWM_CTRL 0x50 /* Control/Config register */ #define STI_INT_EN 0x54 /* Interrupt Enable/Disable register */ +#define STI_INT_STA 0x58 /* Interrupt Status register */ +#define PWM_INT_ACK 0x5c #define PWM_PRESCALE_LOW_MASK 0x0f #define PWM_PRESCALE_HIGH_MASK 0xf0 +#define PWM_CPT_EDGE_MASK 0x03 +#define PWM_INT_ACK_MASK 0x1ff + +#define STI_MAX_CPT_CHANS 4 +#define CPT_DC_MAX 0xff /* Regfield IDs */ enum { /* Bits in PWM_CTRL*/ PWMCLK_PRESCALE_LOW, PWMCLK_PRESCALE_HIGH, + CPTCLK_PRESCALE, PWM_OUT_EN, + PWM_CPT_EN, PWM_CPT_INT_EN, + PWM_CPT_INT_STAT, /* Keep last */ MAX_REGFIELDS }; +/* Each capture input can be programmed to detect rising-edge, falling-edge, + * either edge or neither egde + */ +enum sti_cpt_edge { + CPT_EDGE_DISABLED, + CPT_EDGE_RISING, + CPT_EDGE_FALLING, + CPT_EDGE_BOTH, +}; + struct sti_pwm_compat_data { const struct reg_field *reg_fields; unsigned int num_chan; @@ -69,8 +91,11 @@ struct sti_pwm_chip { static const struct reg_field sti_pwm_regfields[MAX_REGFIELDS] = { [PWMCLK_PRESCALE_LOW] = REG_FIELD(STI_PWM_CTRL, 0, 3), [PWMCLK_PRESCALE_HIGH] = REG_FIELD(STI_PWM_CTRL, 11, 14), + [CPTCLK_PRESCALE] = REG_FIELD(STI_PWM_CTRL, 4, 8), [PWM_OUT_EN] = REG_FIELD(STI_PWM_CTRL, 9, 9), + [PWM_CPT_EN] = REG_FIELD(STI_PWM_CTRL, 10, 10), [PWM_CPT_INT_EN] = REG_FIELD(STI_INT_EN, 1, 4), + [PWM_CPT_INT_STAT] = REG_FIELD(STI_INT_STA, 1, 4), }; static inline struct sti_pwm_chip *to_sti_pwmchip(struct pwm_chip *chip)