| Message ID | f044eb44654522801d4a93e94918a32c72c4c49f.1718980864.git.lorenzo@kernel.org |
|---|---|
| State | New |
| Headers | show |
| Series | Add Airoha EN7581 PCIE support | expand |
On Fri, Jun 21, 2024 at 04:48:50PM +0200, Lorenzo Bianconi wrote: > Introduce support for Airoha EN7581 pcie controller to mediatek-gen3 > pcie controller driver. s/pcie/PCIe/ (twice) > Tested-by: Zhengping Zhang <zhengping.zhang@airoha.com> > Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> > --- > drivers/pci/controller/Kconfig | 2 +- > drivers/pci/controller/pcie-mediatek-gen3.c | 84 ++++++++++++++++++++- > 2 files changed, 84 insertions(+), 2 deletions(-) > > diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig > index e534c02ee34f..3bd6c9430010 100644 > --- a/drivers/pci/controller/Kconfig > +++ b/drivers/pci/controller/Kconfig > @@ -196,7 +196,7 @@ config PCIE_MEDIATEK > > config PCIE_MEDIATEK_GEN3 > tristate "MediaTek Gen3 PCIe controller" > - depends on ARCH_MEDIATEK || COMPILE_TEST > + depends on ARCH_AIROHA || ARCH_MEDIATEK || COMPILE_TEST > depends on PCI_MSI > help > Adds support for PCIe Gen3 MAC controller for MediaTek SoCs. > diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c > index 9842617795a9..2dacfed665c6 100644 > --- a/drivers/pci/controller/pcie-mediatek-gen3.c > +++ b/drivers/pci/controller/pcie-mediatek-gen3.c > @@ -7,6 +7,7 @@ > */ > > #include <linux/clk.h> > +#include <linux/clk-provider.h> > #include <linux/delay.h> > #include <linux/iopoll.h> > #include <linux/irq.h> > @@ -21,6 +22,8 @@ > #include <linux/pm_domain.h> > #include <linux/pm_runtime.h> > #include <linux/reset.h> > +#include <linux/of_pci.h> > +#include <linux/of_device.h> Existing list of includes is sorted. Preserve that sorted order. > +static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) > +{ > + struct device *dev = pcie->dev; > + int err; > + > + writel_relaxed(0x23020133, pcie->base + 0x10044); > + writel_relaxed(0x50500032, pcie->base + 0x15030); > + writel_relaxed(0x50500032, pcie->base + 0x15130); Magic. Needs #defines at least for the registers. These offsets are HUGE, far bigger than the existing offsets: #define PCIE_CFGNUM_REG 0x140 #define PCIE_CFG_OFFSET_ADDR 0x1000 #define PCIE_TRANS_TABLE_BASE_REG 0x800 #define PCIE_MSI_SET_BASE_REG 0xc00 #define PCIE_MSI_SET_ADDR_HI_BASE 0xc80 #define PCIE_MSI_SET_ENABLE_REG 0x190 #define PCIE_INT_ENABLE_REG 0x180 #define PCIE_SETTING_REG 0x80 #define PCIE_PCI_IDS_1 0x9c #define PCIE_MISC_CTRL_REG 0x348 #define PCIE_RST_CTRL_REG 0x148 #define PCIE_LINK_STATUS_REG 0x154 #define PCIE_LTSSM_STATUS_REG 0x150 #define PCIE_INT_STATUS_REG 0x184 > + err = phy_init(pcie->phy); > + if (err) { > + dev_err(dev, "failed to initialize PHY\n"); > + return err; > + } > + mdelay(30); Source? Cite the spec that requires this delay and add a #define if possible. > + err = phy_power_on(pcie->phy); > + if (err) { > + dev_err(dev, "failed to power on PHY\n"); > + goto err_phy_on; > + } > + > + err = reset_control_bulk_deassert(pcie->soc->phy_resets.num_rsts, > + pcie->phy_resets); > + if (err) { > + dev_err(dev, "failed to deassert PHYs\n"); > + goto err_phy_deassert; > + } > + usleep_range(5000, 10000); Source? > + pm_runtime_enable(dev); > + pm_runtime_get_sync(dev); > + > + err = clk_bulk_prepare(pcie->num_clks, pcie->clks); > + if (err) { > + dev_err(dev, "failed to prepare clock\n"); > + goto err_clk_prepare; > + } > + > + writel_relaxed(0x41474147, pcie->base + PCIE_EQ_PRESET_01_REF); > + writel_relaxed(0x1018020f, pcie->base + PCIE_PIPE4_PIE8_REG); > + mdelay(10); Source?
> On Fri, Jun 21, 2024 at 04:48:50PM +0200, Lorenzo Bianconi wrote: > > Introduce support for Airoha EN7581 pcie controller to mediatek-gen3 > > pcie controller driver. > > s/pcie/PCIe/ (twice) > ack, I will fix them in v2 > > Tested-by: Zhengping Zhang <zhengping.zhang@airoha.com> > > Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> > > --- > > drivers/pci/controller/Kconfig | 2 +- > > drivers/pci/controller/pcie-mediatek-gen3.c | 84 ++++++++++++++++++++- > > 2 files changed, 84 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig > > index e534c02ee34f..3bd6c9430010 100644 > > --- a/drivers/pci/controller/Kconfig > > +++ b/drivers/pci/controller/Kconfig > > @@ -196,7 +196,7 @@ config PCIE_MEDIATEK > > > > config PCIE_MEDIATEK_GEN3 > > tristate "MediaTek Gen3 PCIe controller" > > - depends on ARCH_MEDIATEK || COMPILE_TEST > > + depends on ARCH_AIROHA || ARCH_MEDIATEK || COMPILE_TEST > > depends on PCI_MSI > > help > > Adds support for PCIe Gen3 MAC controller for MediaTek SoCs. > > diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c > > index 9842617795a9..2dacfed665c6 100644 > > --- a/drivers/pci/controller/pcie-mediatek-gen3.c > > +++ b/drivers/pci/controller/pcie-mediatek-gen3.c > > @@ -7,6 +7,7 @@ > > */ > > > > #include <linux/clk.h> > > +#include <linux/clk-provider.h> > > #include <linux/delay.h> > > #include <linux/iopoll.h> > > #include <linux/irq.h> > > @@ -21,6 +22,8 @@ > > #include <linux/pm_domain.h> > > #include <linux/pm_runtime.h> > > #include <linux/reset.h> > > +#include <linux/of_pci.h> > > +#include <linux/of_device.h> > > Existing list of includes is sorted. Preserve that sorted order. ack, I will fix them in v2 > > > +static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) > > +{ > > + struct device *dev = pcie->dev; > > + int err; > > + > > + writel_relaxed(0x23020133, pcie->base + 0x10044); > > + writel_relaxed(0x50500032, pcie->base + 0x15030); > > + writel_relaxed(0x50500032, pcie->base + 0x15130); > > Magic. Needs #defines at least for the registers. These offsets are > HUGE, far bigger than the existing offsets: ack. Anyway they are in pcie mapped regions (I have not posted the dts changes yet): pcie0: reg = <0x0 0x1fc00000 0x0 0x20000>; pcie1: reg = <0x0 0x1fc20000 0x0 0x20000>; But they are undocumented. I will try to get some info for them. > > #define PCIE_CFGNUM_REG 0x140 > #define PCIE_CFG_OFFSET_ADDR 0x1000 > #define PCIE_TRANS_TABLE_BASE_REG 0x800 > #define PCIE_MSI_SET_BASE_REG 0xc00 > #define PCIE_MSI_SET_ADDR_HI_BASE 0xc80 > #define PCIE_MSI_SET_ENABLE_REG 0x190 > #define PCIE_INT_ENABLE_REG 0x180 > #define PCIE_SETTING_REG 0x80 > #define PCIE_PCI_IDS_1 0x9c > #define PCIE_MISC_CTRL_REG 0x348 > #define PCIE_RST_CTRL_REG 0x148 > #define PCIE_LINK_STATUS_REG 0x154 > #define PCIE_LTSSM_STATUS_REG 0x150 > #define PCIE_INT_STATUS_REG 0x184 > > > + err = phy_init(pcie->phy); > > + if (err) { > > + dev_err(dev, "failed to initialize PHY\n"); > > + return err; > > + } > > + mdelay(30); > > Source? Cite the spec that requires this delay and add a #define if > possible. They are undocumented in the vendor sdk, I will try some info for them (and even for the ones below). Regards, Lorenzo > > > + err = phy_power_on(pcie->phy); > > + if (err) { > > + dev_err(dev, "failed to power on PHY\n"); > > + goto err_phy_on; > > + } > > + > > + err = reset_control_bulk_deassert(pcie->soc->phy_resets.num_rsts, > > + pcie->phy_resets); > > + if (err) { > > + dev_err(dev, "failed to deassert PHYs\n"); > > + goto err_phy_deassert; > > + } > > + usleep_range(5000, 10000); > > Source? > > > + pm_runtime_enable(dev); > > + pm_runtime_get_sync(dev); > > + > > + err = clk_bulk_prepare(pcie->num_clks, pcie->clks); > > + if (err) { > > + dev_err(dev, "failed to prepare clock\n"); > > + goto err_clk_prepare; > > + } > > + > > + writel_relaxed(0x41474147, pcie->base + PCIE_EQ_PRESET_01_REF); > > + writel_relaxed(0x1018020f, pcie->base + PCIE_PIPE4_PIE8_REG); > > + mdelay(10); > > Source?
Il 21/06/24 16:48, Lorenzo Bianconi ha scritto: > Introduce support for Airoha EN7581 pcie controller to mediatek-gen3 > pcie controller driver. > > Tested-by: Zhengping Zhang <zhengping.zhang@airoha.com> > Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> > --- > drivers/pci/controller/Kconfig | 2 +- > drivers/pci/controller/pcie-mediatek-gen3.c | 84 ++++++++++++++++++++- > 2 files changed, 84 insertions(+), 2 deletions(-) > > diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig > index e534c02ee34f..3bd6c9430010 100644 > --- a/drivers/pci/controller/Kconfig > +++ b/drivers/pci/controller/Kconfig > @@ -196,7 +196,7 @@ config PCIE_MEDIATEK > > config PCIE_MEDIATEK_GEN3 > tristate "MediaTek Gen3 PCIe controller" > - depends on ARCH_MEDIATEK || COMPILE_TEST > + depends on ARCH_AIROHA || ARCH_MEDIATEK || COMPILE_TEST > depends on PCI_MSI > help > Adds support for PCIe Gen3 MAC controller for MediaTek SoCs. > diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c > index 9842617795a9..2dacfed665c6 100644 > --- a/drivers/pci/controller/pcie-mediatek-gen3.c > +++ b/drivers/pci/controller/pcie-mediatek-gen3.c > @@ -7,6 +7,7 @@ > */ > > #include <linux/clk.h> > +#include <linux/clk-provider.h> > #include <linux/delay.h> > #include <linux/iopoll.h> > #include <linux/irq.h> > @@ -21,6 +22,8 @@ > #include <linux/pm_domain.h> > #include <linux/pm_runtime.h> > #include <linux/reset.h> > +#include <linux/of_pci.h> > +#include <linux/of_device.h> > > #include "../pci.h" > > @@ -29,6 +32,7 @@ > #define PCI_CLASS(class) (class << 8) > #define PCIE_RC_MODE BIT(0) > > +#define PCIE_EQ_PRESET_01_REF 0x100 > #define PCIE_CFGNUM_REG 0x140 > #define PCIE_CFG_DEVFN(devfn) ((devfn) & GENMASK(7, 0)) > #define PCIE_CFG_BUS(bus) (((bus) << 8) & GENMASK(15, 8)) > @@ -68,6 +72,7 @@ > #define PCIE_MSI_SET_ENABLE_REG 0x190 > #define PCIE_MSI_SET_ENABLE GENMASK(PCIE_MSI_SET_NUM - 1, 0) > > +#define PCIE_PIPE4_PIE8_REG 0x338 > #define PCIE_MSI_SET_BASE_REG 0xc00 > #define PCIE_MSI_SET_OFFSET 0x10 > #define PCIE_MSI_SET_STATUS_OFFSET 0x04 > @@ -100,7 +105,7 @@ > #define PCIE_ATR_TLP_TYPE_MEM PCIE_ATR_TLP_TYPE(0) > #define PCIE_ATR_TLP_TYPE_IO PCIE_ATR_TLP_TYPE(2) > > -#define MAX_NUM_PHY_RSTS 1 > +#define MAX_NUM_PHY_RSTS 3 > > struct mtk_gen3_pcie; > > @@ -848,6 +853,72 @@ static int mtk_pcie_parse_port(struct mtk_gen3_pcie *pcie) > return 0; > } > > +static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) > +{ > + struct device *dev = pcie->dev; > + int err; > + > + writel_relaxed(0x23020133, pcie->base + 0x10044); > + writel_relaxed(0x50500032, pcie->base + 0x15030); > + writel_relaxed(0x50500032, pcie->base + 0x15130); Can anyone from MediaTek/Airoha help to identify those registers and the layout so that we can avoid using magic numbers around? Please. Regards, Angelo > + > + err = phy_init(pcie->phy); > + if (err) { > + dev_err(dev, "failed to initialize PHY\n"); > + return err; > + } > + mdelay(30); > + > + err = phy_power_on(pcie->phy); > + if (err) { > + dev_err(dev, "failed to power on PHY\n"); > + goto err_phy_on; > + } > + > + err = reset_control_bulk_deassert(pcie->soc->phy_resets.num_rsts, > + pcie->phy_resets); > + if (err) { > + dev_err(dev, "failed to deassert PHYs\n"); > + goto err_phy_deassert; > + } > + usleep_range(5000, 10000); > + > + pm_runtime_enable(dev); > + pm_runtime_get_sync(dev); > + > + err = clk_bulk_prepare(pcie->num_clks, pcie->clks); > + if (err) { > + dev_err(dev, "failed to prepare clock\n"); > + goto err_clk_prepare; > + } > + > + writel_relaxed(0x41474147, pcie->base + PCIE_EQ_PRESET_01_REF); > + writel_relaxed(0x1018020f, pcie->base + PCIE_PIPE4_PIE8_REG); > + mdelay(10); > + > + err = clk_bulk_enable(pcie->num_clks, pcie->clks); > + if (err) { > + dev_err(dev, "failed to prepare clock\n"); > + goto err_clk_enable; > + } > + > + return 0; > + > +err_clk_enable: > + clk_bulk_unprepare(pcie->num_clks, pcie->clks); > +err_clk_prepare: > + pm_runtime_put_sync(dev); > + pm_runtime_disable(dev); > + reset_control_bulk_assert(pcie->soc->phy_resets.num_rsts, > + pcie->phy_resets); > +err_phy_deassert: > + phy_power_off(pcie->phy); > +err_phy_on: > + phy_exit(pcie->phy); > + > + return err; > +} > + > static int mtk_pcie_power_up(struct mtk_gen3_pcie *pcie) > { > struct device *dev = pcie->dev; > @@ -1117,8 +1188,19 @@ static const struct mtk_pcie_soc mtk_pcie_soc_mt8192 = { > }, > }; > > +static const struct mtk_pcie_soc mtk_pcie_soc_en7581 = { > + .power_up = mtk_pcie_en7581_power_up, > + .phy_resets = { > + .id[0] = "phy-lane0", > + .id[1] = "phy-lane1", > + .id[2] = "phy-lane2", > + .num_rsts = 3, > + }, > +}; > + > static const struct of_device_id mtk_pcie_of_match[] = { > { .compatible = "mediatek,mt8192-pcie", .data = &mtk_pcie_soc_mt8192 }, > + { .compatible = "airoha,en7581-pcie", .data = &mtk_pcie_soc_en7581 }, > {}, > }; > MODULE_DEVICE_TABLE(of, mtk_pcie_of_match);
diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig index e534c02ee34f..3bd6c9430010 100644 --- a/drivers/pci/controller/Kconfig +++ b/drivers/pci/controller/Kconfig @@ -196,7 +196,7 @@ config PCIE_MEDIATEK config PCIE_MEDIATEK_GEN3 tristate "MediaTek Gen3 PCIe controller" - depends on ARCH_MEDIATEK || COMPILE_TEST + depends on ARCH_AIROHA || ARCH_MEDIATEK || COMPILE_TEST depends on PCI_MSI help Adds support for PCIe Gen3 MAC controller for MediaTek SoCs. diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c index 9842617795a9..2dacfed665c6 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -7,6 +7,7 @@ */ #include <linux/clk.h> +#include <linux/clk-provider.h> #include <linux/delay.h> #include <linux/iopoll.h> #include <linux/irq.h> @@ -21,6 +22,8 @@ #include <linux/pm_domain.h> #include <linux/pm_runtime.h> #include <linux/reset.h> +#include <linux/of_pci.h> +#include <linux/of_device.h> #include "../pci.h" @@ -29,6 +32,7 @@ #define PCI_CLASS(class) (class << 8) #define PCIE_RC_MODE BIT(0) +#define PCIE_EQ_PRESET_01_REF 0x100 #define PCIE_CFGNUM_REG 0x140 #define PCIE_CFG_DEVFN(devfn) ((devfn) & GENMASK(7, 0)) #define PCIE_CFG_BUS(bus) (((bus) << 8) & GENMASK(15, 8)) @@ -68,6 +72,7 @@ #define PCIE_MSI_SET_ENABLE_REG 0x190 #define PCIE_MSI_SET_ENABLE GENMASK(PCIE_MSI_SET_NUM - 1, 0) +#define PCIE_PIPE4_PIE8_REG 0x338 #define PCIE_MSI_SET_BASE_REG 0xc00 #define PCIE_MSI_SET_OFFSET 0x10 #define PCIE_MSI_SET_STATUS_OFFSET 0x04 @@ -100,7 +105,7 @@ #define PCIE_ATR_TLP_TYPE_MEM PCIE_ATR_TLP_TYPE(0) #define PCIE_ATR_TLP_TYPE_IO PCIE_ATR_TLP_TYPE(2) -#define MAX_NUM_PHY_RSTS 1 +#define MAX_NUM_PHY_RSTS 3 struct mtk_gen3_pcie; @@ -848,6 +853,72 @@ static int mtk_pcie_parse_port(struct mtk_gen3_pcie *pcie) return 0; } +static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) +{ + struct device *dev = pcie->dev; + int err; + + writel_relaxed(0x23020133, pcie->base + 0x10044); + writel_relaxed(0x50500032, pcie->base + 0x15030); + writel_relaxed(0x50500032, pcie->base + 0x15130); + + err = phy_init(pcie->phy); + if (err) { + dev_err(dev, "failed to initialize PHY\n"); + return err; + } + mdelay(30); + + err = phy_power_on(pcie->phy); + if (err) { + dev_err(dev, "failed to power on PHY\n"); + goto err_phy_on; + } + + err = reset_control_bulk_deassert(pcie->soc->phy_resets.num_rsts, + pcie->phy_resets); + if (err) { + dev_err(dev, "failed to deassert PHYs\n"); + goto err_phy_deassert; + } + usleep_range(5000, 10000); + + pm_runtime_enable(dev); + pm_runtime_get_sync(dev); + + err = clk_bulk_prepare(pcie->num_clks, pcie->clks); + if (err) { + dev_err(dev, "failed to prepare clock\n"); + goto err_clk_prepare; + } + + writel_relaxed(0x41474147, pcie->base + PCIE_EQ_PRESET_01_REF); + writel_relaxed(0x1018020f, pcie->base + PCIE_PIPE4_PIE8_REG); + mdelay(10); + + err = clk_bulk_enable(pcie->num_clks, pcie->clks); + if (err) { + dev_err(dev, "failed to prepare clock\n"); + goto err_clk_enable; + } + + return 0; + +err_clk_enable: + clk_bulk_unprepare(pcie->num_clks, pcie->clks); +err_clk_prepare: + pm_runtime_put_sync(dev); + pm_runtime_disable(dev); + reset_control_bulk_assert(pcie->soc->phy_resets.num_rsts, + pcie->phy_resets); +err_phy_deassert: + phy_power_off(pcie->phy); +err_phy_on: + phy_exit(pcie->phy); + + return err; +} + static int mtk_pcie_power_up(struct mtk_gen3_pcie *pcie) { struct device *dev = pcie->dev; @@ -1117,8 +1188,19 @@ static const struct mtk_pcie_soc mtk_pcie_soc_mt8192 = { }, }; +static const struct mtk_pcie_soc mtk_pcie_soc_en7581 = { + .power_up = mtk_pcie_en7581_power_up, + .phy_resets = { + .id[0] = "phy-lane0", + .id[1] = "phy-lane1", + .id[2] = "phy-lane2", + .num_rsts = 3, + }, +}; + static const struct of_device_id mtk_pcie_of_match[] = { { .compatible = "mediatek,mt8192-pcie", .data = &mtk_pcie_soc_mt8192 }, + { .compatible = "airoha,en7581-pcie", .data = &mtk_pcie_soc_en7581 }, {}, }; MODULE_DEVICE_TABLE(of, mtk_pcie_of_match);