Message ID | dbfaccc9902e43b659584e4638a26549a363292a.1526314398.git.gustavo.pimentel@synopsys.com |
---|---|
State | Superseded |
Headers | show |
Series | Add DesignWare EP support | expand |
Às 5:17 PM de 5/14/2018, Gustavo Pimentel escreveu: > The PCIe controller dual mode is capable of operating in RC mode as well > as EP mode by configuration option. Till now only RC mode was supported, > with this patch is add EP support to the DesignWare driver. > > Add new property on pci_epc structure which allow to configure > pci_epf_test driver accordingly to the controller specific requirements. > > Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> > Acked-by: Kishon Vijay Abraham I <kishon@ti.com> > --- > drivers/pci/dwc/Kconfig | 41 +++++-- > drivers/pci/dwc/pcie-designware-ep.c | 3 + > drivers/pci/dwc/pcie-designware-plat.c | 149 ++++++++++++++++++++++++-- > drivers/pci/endpoint/functions/pci-epf-test.c | 7 ++ > include/linux/pci-epc.h | 8 ++ > 5 files changed, 187 insertions(+), 21 deletions(-) > > diff --git a/drivers/pci/dwc/Kconfig b/drivers/pci/dwc/Kconfig > index 2f3f5c5..62f7cdf 100644 > --- a/drivers/pci/dwc/Kconfig > +++ b/drivers/pci/dwc/Kconfig > @@ -7,8 +7,7 @@ config PCIE_DW > > config PCIE_DW_HOST > bool > - depends on PCI > - depends on PCI_MSI_IRQ_DOMAIN > + depends on PCI && PCI_MSI_IRQ_DOMAIN > select PCIE_DW > > config PCIE_DW_EP > @@ -51,17 +50,37 @@ config PCI_DRA7XX_EP > This uses the DesignWare core. > > config PCIE_DW_PLAT > - bool "Platform bus based DesignWare PCIe Controller" > - depends on PCI > - depends on PCI_MSI_IRQ_DOMAIN > - select PCIE_DW_HOST > - ---help--- > - This selects the DesignWare PCIe controller support. Select this if > - you have a PCIe controller on Platform bus. > + bool > > - If you have a controller with this interface, say Y or M here. > +config PCIE_DW_PLAT_HOST > + bool "Platform bus based DesignWare PCIe Controller - Host mode" > + depends on PCI && PCI_MSI_IRQ_DOMAIN > + select PCIE_DW_HOST > + select PCIE_DW_PLAT > + default y > + help > + Enables support for the PCIe controller in the Designware IP to > + work in host mode. There are two instances of PCIe controller in > + Designware IP. > + This controller can work either as EP or RC. In order to enable > + host-specific features PCIE_DW_PLAT_HOST must be selected and in > + order to enable device-specific features PCI_DW_PLAT_EP must be > + selected. > > - If unsure, say N. > +config PCIE_DW_PLAT_EP > + bool "Platform bus based DesignWare PCIe Controller - Endpoint mode" > + depends on PCI && PCI_MSI_IRQ_DOMAIN > + depends on PCI_ENDPOINT > + select PCIE_DW_EP > + select PCIE_DW_PLAT > + help > + Enables support for the PCIe controller in the Designware IP to > + work in endpoint mode. There are two instances of PCIe controller > + in Designware IP. > + This controller can work either as EP or RC. In order to enable > + host-specific features PCIE_DW_PLAT_HOST must be selected and in > + order to enable device-specific features PCI_DW_PLAT_EP must be > + selected. > > config PCI_EXYNOS > bool "Samsung Exynos PCIe controller" > diff --git a/drivers/pci/dwc/pcie-designware-ep.c b/drivers/pci/dwc/pcie-designware-ep.c > index f07678b..2c05a08 100644 > --- a/drivers/pci/dwc/pcie-designware-ep.c > +++ b/drivers/pci/dwc/pcie-designware-ep.c > @@ -411,6 +411,9 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) > return -ENOMEM; > } > > + epc->features = EPC_FEATURE_NO_LINKUP_NOTIFIER; > + EPC_FEATURE_SET_BAR(epc->features, BAR0); > + > ep->epc = epc; > epc_set_drvdata(epc, ep); > dw_pcie_setup(pci); > diff --git a/drivers/pci/dwc/pcie-designware-plat.c b/drivers/pci/dwc/pcie-designware-plat.c > index 5416aa8..efc315c 100644 > --- a/drivers/pci/dwc/pcie-designware-plat.c > +++ b/drivers/pci/dwc/pcie-designware-plat.c > @@ -12,19 +12,29 @@ > #include <linux/interrupt.h> > #include <linux/kernel.h> > #include <linux/init.h> > +#include <linux/of_device.h> > #include <linux/of_gpio.h> > #include <linux/pci.h> > #include <linux/platform_device.h> > #include <linux/resource.h> > #include <linux/signal.h> > #include <linux/types.h> > +#include <linux/regmap.h> > > #include "pcie-designware.h" > > struct dw_plat_pcie { > - struct dw_pcie *pci; > + struct dw_pcie *pci; > + struct regmap *regmap; > + enum dw_pcie_device_mode mode; > }; > > +struct dw_plat_pcie_of_data { > + enum dw_pcie_device_mode mode; > +}; > + > +static const struct of_device_id dw_plat_pcie_of_match[]; > + > static int dw_plat_pcie_host_init(struct pcie_port *pp) > { > struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > @@ -42,9 +52,53 @@ static const struct dw_pcie_host_ops dw_plat_pcie_host_ops = { > .host_init = dw_plat_pcie_host_init, > }; > > -static int dw_plat_add_pcie_port(struct pcie_port *pp, > +static int dw_plat_pcie_establish_link(struct dw_pcie *pci) > +{ > + return 0; > +} > + > +static const struct dw_pcie_ops dw_pcie_ops = { > + .start_link = dw_plat_pcie_establish_link, > +}; > + > +static void dw_plat_pcie_ep_init(struct dw_pcie_ep *ep) > +{ > + struct dw_pcie *pci = to_dw_pcie_from_ep(ep); > + enum pci_barno bar; > + > + for (bar = BAR_0; bar <= BAR_5; bar++) > + dw_pcie_ep_reset_bar(pci, bar); > +} > + > +static int dw_plat_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, > + enum pci_epc_irq_type type, > + u8 interrupt_num) > +{ > + struct dw_pcie *pci = to_dw_pcie_from_ep(ep); > + > + switch (type) { > + case PCI_EPC_IRQ_LEGACY: > + dev_err(pci->dev, "EP cannot trigger legacy IRQs\n"); > + return -EINVAL; > + case PCI_EPC_IRQ_MSI: > + return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num); > + default: > + dev_err(pci->dev, "UNKNOWN IRQ type\n"); > + } > + > + return 0; > +} > + > +static struct dw_pcie_ep_ops pcie_ep_ops = { > + .ep_init = dw_plat_pcie_ep_init, > + .raise_irq = dw_plat_pcie_ep_raise_irq, > +}; > + > +static int dw_plat_add_pcie_port(struct dw_plat_pcie *dw_plat_pcie, > struct platform_device *pdev) > { > + struct dw_pcie *pci = dw_plat_pcie->pci; > + struct pcie_port *pp = &pci->pp; > struct device *dev = &pdev->dev; > int ret; > > @@ -63,15 +117,44 @@ static int dw_plat_add_pcie_port(struct pcie_port *pp, > > ret = dw_pcie_host_init(pp); > if (ret) { > - dev_err(dev, "failed to initialize host\n"); > + dev_err(dev, "Failed to initialize host\n"); > return ret; > } > > return 0; > } > > -static const struct dw_pcie_ops dw_pcie_ops = { > -}; > +static int dw_plat_add_pcie_ep(struct dw_plat_pcie *dw_plat_pcie, > + struct platform_device *pdev) > +{ > + int ret; > + struct dw_pcie_ep *ep; > + struct resource *res; > + struct device *dev = &pdev->dev; > + struct dw_pcie *pci = dw_plat_pcie->pci; > + > + ep = &pci->ep; > + ep->ops = &pcie_ep_ops; > + > + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi2"); > + pci->dbi_base2 = devm_ioremap_resource(dev, res); > + if (IS_ERR(pci->dbi_base2)) > + return PTR_ERR(pci->dbi_base2); > + > + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space"); > + if (!res) > + return -EINVAL; > + > + ep->phys_base = res->start; > + ep->addr_size = resource_size(res); > + > + ret = dw_pcie_ep_init(ep); > + if (ret) { > + dev_err(dev, "Failed to initialize endpoint\n"); > + return ret; > + } > + return 0; > +} > > static int dw_plat_pcie_probe(struct platform_device *pdev) > { > @@ -80,6 +163,16 @@ static int dw_plat_pcie_probe(struct platform_device *pdev) > struct dw_pcie *pci; > struct resource *res; /* Resource from DT */ > int ret; > + const struct of_device_id *match; > + const struct dw_plat_pcie_of_data *data; > + enum dw_pcie_device_mode mode; > + > + match = of_match_device(dw_plat_pcie_of_match, dev); > + if (!match) > + return -EINVAL; > + > + data = (struct dw_plat_pcie_of_data *)match->data; > + mode = (enum dw_pcie_device_mode)data->mode; > > dw_plat_pcie = devm_kzalloc(dev, sizeof(*dw_plat_pcie), GFP_KERNEL); > if (!dw_plat_pcie) > @@ -93,23 +186,59 @@ static int dw_plat_pcie_probe(struct platform_device *pdev) > pci->ops = &dw_pcie_ops; > > dw_plat_pcie->pci = pci; > + dw_plat_pcie->mode = mode; > + > + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); > + if (!res) > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > > - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > pci->dbi_base = devm_ioremap_resource(dev, res); > if (IS_ERR(pci->dbi_base)) > return PTR_ERR(pci->dbi_base); > > platform_set_drvdata(pdev, dw_plat_pcie); > > - ret = dw_plat_add_pcie_port(&pci->pp, pdev); > - if (ret < 0) > - return ret; > + switch (dw_plat_pcie->mode) { > + case DW_PCIE_RC_TYPE: > + if (!IS_ENABLED(CONFIG_PCIE_DW_PLAT_HOST)) > + return -ENODEV; > + > + ret = dw_plat_add_pcie_port(dw_plat_pcie, pdev); > + if (ret < 0) > + return ret; > + break; > + case DW_PCIE_EP_TYPE: > + if (!IS_ENABLED(CONFIG_PCIE_DW_PLAT_EP)) > + return -ENODEV; > + > + ret = dw_plat_add_pcie_ep(dw_plat_pcie, pdev); > + if (ret < 0) > + return ret; > + break; > + default: > + dev_err(dev, "INVALID device type %d\n", dw_plat_pcie->mode); > + } > > return 0; > } > > +static const struct dw_plat_pcie_of_data dw_plat_pcie_rc_of_data = { > + .mode = DW_PCIE_RC_TYPE, > +}; > + > +static const struct dw_plat_pcie_of_data dw_plat_pcie_ep_of_data = { > + .mode = DW_PCIE_EP_TYPE, > +}; > + > static const struct of_device_id dw_plat_pcie_of_match[] = { > - { .compatible = "snps,dw-pcie", }, > + { > + .compatible = "snps,dw-pcie", > + .data = &dw_plat_pcie_rc_of_data, > + }, > + { > + .compatible = "snps,dw-pcie-ep", > + .data = &dw_plat_pcie_ep_of_data, > + }, > {}, > }; > > diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c b/drivers/pci/endpoint/functions/pci-epf-test.c > index 7cef851..bee401d 100644 > --- a/drivers/pci/endpoint/functions/pci-epf-test.c > +++ b/drivers/pci/endpoint/functions/pci-epf-test.c > @@ -435,6 +435,13 @@ static int pci_epf_test_bind(struct pci_epf *epf) > if (WARN_ON_ONCE(!epc)) > return -EINVAL; > > + if (epc->features & EPC_FEATURE_NO_LINKUP_NOTIFIER) > + epf_test->linkup_notifier = false; > + else > + epf_test->linkup_notifier = true; > + > + epf_test->test_reg_bar = EPC_FEATURE_GET_BAR(epc->features); > + > ret = pci_epc_write_header(epc, epf->func_no, header); > if (ret) { > dev_err(dev, "configuration header write failed\n"); > diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h > index af657ca..243eaa5 100644 > --- a/include/linux/pci-epc.h > +++ b/include/linux/pci-epc.h > @@ -90,8 +90,16 @@ struct pci_epc { > struct config_group *group; > /* spinlock to protect against concurrent access of EP controller */ > spinlock_t lock; > + unsigned int features; > }; > > +#define EPC_FEATURE_NO_LINKUP_NOTIFIER BIT(0) > +#define EPC_FEATURE_BAR_MASK (BIT(1) | BIT(2) | BIT(3)) > +#define EPC_FEATURE_SET_BAR(features, bar) \ > + (features |= (EPC_FEATURE_BAR_MASK & (bar << 1))) > +#define EPC_FEATURE_GET_BAR(features) \ > + ((features & EPC_FEATURE_BAR_MASK) >> 1) > + > #define to_pci_epc(device) container_of((device), struct pci_epc, dev) > > #define pci_epc_create(dev, ops) \ > Acked-by: Joao Pinto <jpinto@synopsys.com>
Hi Gustavo, Thank you for the patch! Yet something to improve: [auto build test ERROR on pci/next] [also build test ERROR on v4.17-rc5 next-20180514] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux/commits/Gustavo-Pimentel/Add-DesignWare-EP-support/20180515-072113 base: https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git next config: i386-allmodconfig (attached as .config) compiler: gcc-7 (Debian 7.3.0-16) 7.3.0 reproduce: # save the attached .config to linux build tree make ARCH=i386 All errors (new ones prefixed by >>): In file included from drivers/pci/dwc/pcie-designware.h:19:0, from drivers/pci/dwc/pcie-designware-ep.c:11: drivers/pci/dwc/pcie-designware-ep.c: In function 'dw_pcie_ep_init': >> drivers/pci/dwc/pcie-designware-ep.c:415:37: error: 'BAR0' undeclared (first use in this function); did you mean 'BAR_0'? EPC_FEATURE_SET_BAR(epc->features, BAR0); ^ include/linux/pci-epc.h:99:41: note: in definition of macro 'EPC_FEATURE_SET_BAR' (features |= (EPC_FEATURE_BAR_MASK & (bar << 1))) ^~~ drivers/pci/dwc/pcie-designware-ep.c:415:37: note: each undeclared identifier is reported only once for each function it appears in EPC_FEATURE_SET_BAR(epc->features, BAR0); ^ include/linux/pci-epc.h:99:41: note: in definition of macro 'EPC_FEATURE_SET_BAR' (features |= (EPC_FEATURE_BAR_MASK & (bar << 1))) ^~~ vim +415 drivers/pci/dwc/pcie-designware-ep.c 334 335 int dw_pcie_ep_init(struct dw_pcie_ep *ep) 336 { 337 int ret; 338 void *addr; 339 struct pci_epc *epc; 340 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 341 struct device *dev = pci->dev; 342 struct device_node *np = dev->of_node; 343 344 if (!pci->dbi_base || !pci->dbi_base2) { 345 dev_err(dev, "dbi_base/dbi_base2 is not populated\n"); 346 return -EINVAL; 347 } 348 349 ret = of_property_read_u32(np, "num-ib-windows", &ep->num_ib_windows); 350 if (ret < 0) { 351 dev_err(dev, "unable to read *num-ib-windows* property\n"); 352 return ret; 353 } 354 if (ep->num_ib_windows > MAX_IATU_IN) { 355 dev_err(dev, "invalid *num-ib-windows*\n"); 356 return -EINVAL; 357 } 358 359 ret = of_property_read_u32(np, "num-ob-windows", &ep->num_ob_windows); 360 if (ret < 0) { 361 dev_err(dev, "unable to read *num-ob-windows* property\n"); 362 return ret; 363 } 364 if (ep->num_ob_windows > MAX_IATU_OUT) { 365 dev_err(dev, "invalid *num-ob-windows*\n"); 366 return -EINVAL; 367 } 368 369 ep->ib_window_map = devm_kzalloc(dev, sizeof(long) * 370 BITS_TO_LONGS(ep->num_ib_windows), 371 GFP_KERNEL); 372 if (!ep->ib_window_map) 373 return -ENOMEM; 374 375 ep->ob_window_map = devm_kzalloc(dev, sizeof(long) * 376 BITS_TO_LONGS(ep->num_ob_windows), 377 GFP_KERNEL); 378 if (!ep->ob_window_map) 379 return -ENOMEM; 380 381 addr = devm_kzalloc(dev, sizeof(phys_addr_t) * ep->num_ob_windows, 382 GFP_KERNEL); 383 if (!addr) 384 return -ENOMEM; 385 ep->outbound_addr = addr; 386 387 if (ep->ops->ep_init) 388 ep->ops->ep_init(ep); 389 390 epc = devm_pci_epc_create(dev, &epc_ops); 391 if (IS_ERR(epc)) { 392 dev_err(dev, "failed to create epc device\n"); 393 return PTR_ERR(epc); 394 } 395 396 ret = of_property_read_u8(np, "max-functions", &epc->max_functions); 397 if (ret < 0) 398 epc->max_functions = 1; 399 400 ret = __pci_epc_mem_init(epc, ep->phys_base, ep->addr_size, 401 ep->page_size); 402 if (ret < 0) { 403 dev_err(dev, "Failed to initialize address space\n"); 404 return ret; 405 } 406 407 ep->msi_mem = pci_epc_mem_alloc_addr(epc, &ep->msi_mem_phys, 408 epc->mem->page_size); 409 if (!ep->msi_mem) { 410 dev_err(dev, "Failed to reserve memory for MSI\n"); 411 return -ENOMEM; 412 } 413 414 epc->features = EPC_FEATURE_NO_LINKUP_NOTIFIER; > 415 EPC_FEATURE_SET_BAR(epc->features, BAR0); --- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation
diff --git a/drivers/pci/dwc/Kconfig b/drivers/pci/dwc/Kconfig index 2f3f5c5..62f7cdf 100644 --- a/drivers/pci/dwc/Kconfig +++ b/drivers/pci/dwc/Kconfig @@ -7,8 +7,7 @@ config PCIE_DW config PCIE_DW_HOST bool - depends on PCI - depends on PCI_MSI_IRQ_DOMAIN + depends on PCI && PCI_MSI_IRQ_DOMAIN select PCIE_DW config PCIE_DW_EP @@ -51,17 +50,37 @@ config PCI_DRA7XX_EP This uses the DesignWare core. config PCIE_DW_PLAT - bool "Platform bus based DesignWare PCIe Controller" - depends on PCI - depends on PCI_MSI_IRQ_DOMAIN - select PCIE_DW_HOST - ---help--- - This selects the DesignWare PCIe controller support. Select this if - you have a PCIe controller on Platform bus. + bool - If you have a controller with this interface, say Y or M here. +config PCIE_DW_PLAT_HOST + bool "Platform bus based DesignWare PCIe Controller - Host mode" + depends on PCI && PCI_MSI_IRQ_DOMAIN + select PCIE_DW_HOST + select PCIE_DW_PLAT + default y + help + Enables support for the PCIe controller in the Designware IP to + work in host mode. There are two instances of PCIe controller in + Designware IP. + This controller can work either as EP or RC. In order to enable + host-specific features PCIE_DW_PLAT_HOST must be selected and in + order to enable device-specific features PCI_DW_PLAT_EP must be + selected. - If unsure, say N. +config PCIE_DW_PLAT_EP + bool "Platform bus based DesignWare PCIe Controller - Endpoint mode" + depends on PCI && PCI_MSI_IRQ_DOMAIN + depends on PCI_ENDPOINT + select PCIE_DW_EP + select PCIE_DW_PLAT + help + Enables support for the PCIe controller in the Designware IP to + work in endpoint mode. There are two instances of PCIe controller + in Designware IP. + This controller can work either as EP or RC. In order to enable + host-specific features PCIE_DW_PLAT_HOST must be selected and in + order to enable device-specific features PCI_DW_PLAT_EP must be + selected. config PCI_EXYNOS bool "Samsung Exynos PCIe controller" diff --git a/drivers/pci/dwc/pcie-designware-ep.c b/drivers/pci/dwc/pcie-designware-ep.c index f07678b..2c05a08 100644 --- a/drivers/pci/dwc/pcie-designware-ep.c +++ b/drivers/pci/dwc/pcie-designware-ep.c @@ -411,6 +411,9 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) return -ENOMEM; } + epc->features = EPC_FEATURE_NO_LINKUP_NOTIFIER; + EPC_FEATURE_SET_BAR(epc->features, BAR0); + ep->epc = epc; epc_set_drvdata(epc, ep); dw_pcie_setup(pci); diff --git a/drivers/pci/dwc/pcie-designware-plat.c b/drivers/pci/dwc/pcie-designware-plat.c index 5416aa8..efc315c 100644 --- a/drivers/pci/dwc/pcie-designware-plat.c +++ b/drivers/pci/dwc/pcie-designware-plat.c @@ -12,19 +12,29 @@ #include <linux/interrupt.h> #include <linux/kernel.h> #include <linux/init.h> +#include <linux/of_device.h> #include <linux/of_gpio.h> #include <linux/pci.h> #include <linux/platform_device.h> #include <linux/resource.h> #include <linux/signal.h> #include <linux/types.h> +#include <linux/regmap.h> #include "pcie-designware.h" struct dw_plat_pcie { - struct dw_pcie *pci; + struct dw_pcie *pci; + struct regmap *regmap; + enum dw_pcie_device_mode mode; }; +struct dw_plat_pcie_of_data { + enum dw_pcie_device_mode mode; +}; + +static const struct of_device_id dw_plat_pcie_of_match[]; + static int dw_plat_pcie_host_init(struct pcie_port *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); @@ -42,9 +52,53 @@ static const struct dw_pcie_host_ops dw_plat_pcie_host_ops = { .host_init = dw_plat_pcie_host_init, }; -static int dw_plat_add_pcie_port(struct pcie_port *pp, +static int dw_plat_pcie_establish_link(struct dw_pcie *pci) +{ + return 0; +} + +static const struct dw_pcie_ops dw_pcie_ops = { + .start_link = dw_plat_pcie_establish_link, +}; + +static void dw_plat_pcie_ep_init(struct dw_pcie_ep *ep) +{ + struct dw_pcie *pci = to_dw_pcie_from_ep(ep); + enum pci_barno bar; + + for (bar = BAR_0; bar <= BAR_5; bar++) + dw_pcie_ep_reset_bar(pci, bar); +} + +static int dw_plat_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, + enum pci_epc_irq_type type, + u8 interrupt_num) +{ + struct dw_pcie *pci = to_dw_pcie_from_ep(ep); + + switch (type) { + case PCI_EPC_IRQ_LEGACY: + dev_err(pci->dev, "EP cannot trigger legacy IRQs\n"); + return -EINVAL; + case PCI_EPC_IRQ_MSI: + return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num); + default: + dev_err(pci->dev, "UNKNOWN IRQ type\n"); + } + + return 0; +} + +static struct dw_pcie_ep_ops pcie_ep_ops = { + .ep_init = dw_plat_pcie_ep_init, + .raise_irq = dw_plat_pcie_ep_raise_irq, +}; + +static int dw_plat_add_pcie_port(struct dw_plat_pcie *dw_plat_pcie, struct platform_device *pdev) { + struct dw_pcie *pci = dw_plat_pcie->pci; + struct pcie_port *pp = &pci->pp; struct device *dev = &pdev->dev; int ret; @@ -63,15 +117,44 @@ static int dw_plat_add_pcie_port(struct pcie_port *pp, ret = dw_pcie_host_init(pp); if (ret) { - dev_err(dev, "failed to initialize host\n"); + dev_err(dev, "Failed to initialize host\n"); return ret; } return 0; } -static const struct dw_pcie_ops dw_pcie_ops = { -}; +static int dw_plat_add_pcie_ep(struct dw_plat_pcie *dw_plat_pcie, + struct platform_device *pdev) +{ + int ret; + struct dw_pcie_ep *ep; + struct resource *res; + struct device *dev = &pdev->dev; + struct dw_pcie *pci = dw_plat_pcie->pci; + + ep = &pci->ep; + ep->ops = &pcie_ep_ops; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi2"); + pci->dbi_base2 = devm_ioremap_resource(dev, res); + if (IS_ERR(pci->dbi_base2)) + return PTR_ERR(pci->dbi_base2); + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space"); + if (!res) + return -EINVAL; + + ep->phys_base = res->start; + ep->addr_size = resource_size(res); + + ret = dw_pcie_ep_init(ep); + if (ret) { + dev_err(dev, "Failed to initialize endpoint\n"); + return ret; + } + return 0; +} static int dw_plat_pcie_probe(struct platform_device *pdev) { @@ -80,6 +163,16 @@ static int dw_plat_pcie_probe(struct platform_device *pdev) struct dw_pcie *pci; struct resource *res; /* Resource from DT */ int ret; + const struct of_device_id *match; + const struct dw_plat_pcie_of_data *data; + enum dw_pcie_device_mode mode; + + match = of_match_device(dw_plat_pcie_of_match, dev); + if (!match) + return -EINVAL; + + data = (struct dw_plat_pcie_of_data *)match->data; + mode = (enum dw_pcie_device_mode)data->mode; dw_plat_pcie = devm_kzalloc(dev, sizeof(*dw_plat_pcie), GFP_KERNEL); if (!dw_plat_pcie) @@ -93,23 +186,59 @@ static int dw_plat_pcie_probe(struct platform_device *pdev) pci->ops = &dw_pcie_ops; dw_plat_pcie->pci = pci; + dw_plat_pcie->mode = mode; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); + if (!res) + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); pci->dbi_base = devm_ioremap_resource(dev, res); if (IS_ERR(pci->dbi_base)) return PTR_ERR(pci->dbi_base); platform_set_drvdata(pdev, dw_plat_pcie); - ret = dw_plat_add_pcie_port(&pci->pp, pdev); - if (ret < 0) - return ret; + switch (dw_plat_pcie->mode) { + case DW_PCIE_RC_TYPE: + if (!IS_ENABLED(CONFIG_PCIE_DW_PLAT_HOST)) + return -ENODEV; + + ret = dw_plat_add_pcie_port(dw_plat_pcie, pdev); + if (ret < 0) + return ret; + break; + case DW_PCIE_EP_TYPE: + if (!IS_ENABLED(CONFIG_PCIE_DW_PLAT_EP)) + return -ENODEV; + + ret = dw_plat_add_pcie_ep(dw_plat_pcie, pdev); + if (ret < 0) + return ret; + break; + default: + dev_err(dev, "INVALID device type %d\n", dw_plat_pcie->mode); + } return 0; } +static const struct dw_plat_pcie_of_data dw_plat_pcie_rc_of_data = { + .mode = DW_PCIE_RC_TYPE, +}; + +static const struct dw_plat_pcie_of_data dw_plat_pcie_ep_of_data = { + .mode = DW_PCIE_EP_TYPE, +}; + static const struct of_device_id dw_plat_pcie_of_match[] = { - { .compatible = "snps,dw-pcie", }, + { + .compatible = "snps,dw-pcie", + .data = &dw_plat_pcie_rc_of_data, + }, + { + .compatible = "snps,dw-pcie-ep", + .data = &dw_plat_pcie_ep_of_data, + }, {}, }; diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c b/drivers/pci/endpoint/functions/pci-epf-test.c index 7cef851..bee401d 100644 --- a/drivers/pci/endpoint/functions/pci-epf-test.c +++ b/drivers/pci/endpoint/functions/pci-epf-test.c @@ -435,6 +435,13 @@ static int pci_epf_test_bind(struct pci_epf *epf) if (WARN_ON_ONCE(!epc)) return -EINVAL; + if (epc->features & EPC_FEATURE_NO_LINKUP_NOTIFIER) + epf_test->linkup_notifier = false; + else + epf_test->linkup_notifier = true; + + epf_test->test_reg_bar = EPC_FEATURE_GET_BAR(epc->features); + ret = pci_epc_write_header(epc, epf->func_no, header); if (ret) { dev_err(dev, "configuration header write failed\n"); diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h index af657ca..243eaa5 100644 --- a/include/linux/pci-epc.h +++ b/include/linux/pci-epc.h @@ -90,8 +90,16 @@ struct pci_epc { struct config_group *group; /* spinlock to protect against concurrent access of EP controller */ spinlock_t lock; + unsigned int features; }; +#define EPC_FEATURE_NO_LINKUP_NOTIFIER BIT(0) +#define EPC_FEATURE_BAR_MASK (BIT(1) | BIT(2) | BIT(3)) +#define EPC_FEATURE_SET_BAR(features, bar) \ + (features |= (EPC_FEATURE_BAR_MASK & (bar << 1))) +#define EPC_FEATURE_GET_BAR(features) \ + ((features & EPC_FEATURE_BAR_MASK) >> 1) + #define to_pci_epc(device) container_of((device), struct pci_epc, dev) #define pci_epc_create(dev, ops) \