From patchwork Mon Jul 14 05:31:47 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 369497 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id B79DD1400A3 for ; Mon, 14 Jul 2014 15:31:48 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752552AbaGNFbs (ORCPT ); Mon, 14 Jul 2014 01:31:48 -0400 Received: from mail-ob0-f174.google.com ([209.85.214.174]:52266 "EHLO mail-ob0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750844AbaGNFbr (ORCPT ); Mon, 14 Jul 2014 01:31:47 -0400 Received: by mail-ob0-f174.google.com with SMTP id vb8so3388919obc.5 for ; Sun, 13 Jul 2014 22:31:47 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:in-reply-to:references:date :message-id:subject:from:to:cc:content-type; bh=KcQJnymoRSrWZDd02nhg1X7R/0mf/SFWA6HqALxDFTo=; b=LzRDNvZYy/Il3H0n0ZEhVR0EIChZVhVhaCH8RIcpfeVZvTlj7MaeYLYgelYou2IIHe ES/kn7bkrVSr8d8MW4k4EDGPI2VEwyX85LsDot2xXCtMfQRpDfhGc7b+Sh0+G+6z74wF +Rup9fOE4wugvgG2cLsbdp/O7U3Oau9yN9DpdFTD+IYbN/C4FsRmTcrt5L/1CwyIpBvs 8YQ9JH7QLULJgL851xpowl1X6LQtWzpsXYOOpzjcejGqNWPplCb+nqhcLOdR33h+2oyk MeOQALxAmkWn1myTuOjcPH5GOkguY/O+M4fcgZJLzfD8lPyKkGaqb3rD48CfTQMCZIbV A4gA== X-Gm-Message-State: ALoCoQn1A0RCHGOmIvlxgoLfkPXwJbiyCcdKv/AAIAaG3c5uwuPQT0eYaoQ3GAbtyhzdEDh5pijk MIME-Version: 1.0 X-Received: by 10.60.123.66 with SMTP id ly2mr15389666oeb.19.1405315907124; Sun, 13 Jul 2014 22:31:47 -0700 (PDT) Received: by 10.182.233.166 with HTTP; Sun, 13 Jul 2014 22:31:47 -0700 (PDT) In-Reply-To: <53BE926A.2070005@ti.com> References: <53BE926A.2070005@ti.com> Date: Mon, 14 Jul 2014 11:01:47 +0530 Message-ID: Subject: Re: [PATCH V9 2/7] phy: Add drivers for PCIe and SATA phy on SPEAr13xx From: Viresh Kumar To: Kishon Vijay Abraham I Cc: Arnd Bergmann , "olof@lixom.net" , "linux-arm-kernel@lists.infradead.org" , spear-devel , Bartlomiej Zolnierkiewicz , Bjorn Helgaas , Mark Nicholson , "linux-pci@vger.kernel.org" , Pratyush Anand Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On 10 July 2014 18:47, Kishon Vijay Abraham I wrote: >> diff --git a/Documentation/devicetree/bindings/phy/st-spear1310-miphy.txt b/Documentation/devicetree/bindings/phy/st-spear1310-miphy.txt >> new file mode 100644 >> index 0000000..b9b281a >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/phy/st-spear1310-miphy.txt > > We generally create a single document for a SoC vendor. So just use st-phy.txt. st-phy may not be appropriate as this is specifically for SPEAr. New binding doc looks like this: --- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/phy/st-spear-miphy.txt b/Documentation/devicetree/bindings/phy/st-spear-miphy.txt new file mode 100644 index 0000000..2a6bfdc --- /dev/null +++ b/Documentation/devicetree/bindings/phy/st-spear-miphy.txt @@ -0,0 +1,15 @@ +ST SPEAr miphy DT details +========================= + +ST Microelectronics SPEAr miphy is a phy controller supporting PCIe and SATA. + +Required properties: +- compatible : should be "st,spear1310-miphy" or "st,spear1340-miphy" +- reg : offset and length of the PHY register set. +- misc: phandle for the syscon node to access misc registers +- #phy-cells : from the generic PHY bindings, must be 1. + - cell[1]: 0 if phy used for SATA, 1 for PCIe. + +Optional properties: +- phy-id: Instance id of the phy. Only required when there are multiple phys + present on a implementation.