| Message ID | 819861d0-1b3a-4722-969c-d2f48b624622@siemens.com |
|---|---|
| State | New |
| Headers | show |
| Series | PCI: keystone: Add workaround for Errata #i2037 (AM65x SR 1.0) | expand |
On Wed, Jun 26, 2024 at 12:10:41AM +0200, Jan Kiszka wrote: > From: Kishon Vijay Abraham I <kishon@ti.com> > > Errata #i2037 in AM65x/DRA80xM Processors Silicon Revision 1.0 > (SPRZ452D_July 2018_Revised December 2019 [1]) mentions when an > inbound PCIe TLP spans more than two internal AXI 128-byte bursts, > the bus may corrupt the packet payload and the corrupt data may > cause associated applications or the processor to hang. > > The workaround for Errata #i2037 is to limit the maximum read > request size and maximum payload size to 128 Bytes. Add workaround > for Errata #i2037 here. The errata and workaround is applicable > only to AM65x SR 1.0 and later versions of the silicon will have > this fixed. > > [1] -> http://www.ti.com/lit/er/sprz452d/sprz452d.pdf > > Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> > Signed-off-by: Achal Verma <a-verma1@ti.com> > Link: https://lore.kernel.org/linux-pci/20210325090026.8843-7-kishon@ti.com/ Please drop the above. It needs to be mentioned as the v1 below the tear-line. > Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> > Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> > --- > > Needed for the IOT2050 PG1 variants. Pending downstream way too long. > > drivers/pci/controller/dwc/pci-keystone.c | 42 +++++++++++++++++++++++ > 1 file changed, 42 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c > index d3a7d14ee685..a04f1087ce91 100644 > --- a/drivers/pci/controller/dwc/pci-keystone.c > +++ b/drivers/pci/controller/dwc/pci-keystone.c > @@ -34,6 +34,11 @@ > #define PCIE_DEVICEID_SHIFT 16 [...] > > + static const struct pci_device_id am6_pci_devids[] = { > + { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_AM654X), > + .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, }, > + { 0, }, > + }; > > if (pci_is_root_bus(bus)) > bridge = dev; > @@ -562,6 +578,32 @@ static void ks_pcie_quirk(struct pci_dev *dev) > pcie_set_readrq(dev, 256); > } > } > + > + /* > + * Memory transactions fail with PCI controller in AM654 PG1.0 > + * when MRRS is set to more than 128 Bytes. Force the MRRS to > + * 128 Bytes in all downstream devices. > + */ Comments on the v1 patch at: https://lore.kernel.org/linux-pci/YF2K6+R1P3SNUoo5@rocinante/ haven't been addressed in this patch. Kindly update the patch based on Krzysztof's feedback on the v1 patch. > + if (pci_match_id(am6_pci_devids, bridge)) { > + bridge_dev = pci_get_host_bridge_device(dev); > + if (!bridge_dev && !bridge_dev->parent) > + return; > + > + ks_pcie = dev_get_drvdata(bridge_dev->parent); > + if (!ks_pcie) > + return; > + > + val = ks_pcie_app_readl(ks_pcie, PID); > + val &= RTL; > + val >>= RTL_SHIFT; > + if (val != AM6_PCI_PG1_RTL_VER) > + return; > + > + if (pcie_get_readrq(dev) > 128) { > + dev_info(&dev->dev, "limiting MRRS to 128\n"); > + pcie_set_readrq(dev, 128); > + } > + } > } > DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, ks_pcie_quirk); Regards, Siddharth.
On 27.06.24 14:24, Siddharth Vadapalli wrote: > On Wed, Jun 26, 2024 at 12:10:41AM +0200, Jan Kiszka wrote: >> From: Kishon Vijay Abraham I <kishon@ti.com> >> >> Errata #i2037 in AM65x/DRA80xM Processors Silicon Revision 1.0 >> (SPRZ452D_July 2018_Revised December 2019 [1]) mentions when an >> inbound PCIe TLP spans more than two internal AXI 128-byte bursts, >> the bus may corrupt the packet payload and the corrupt data may >> cause associated applications or the processor to hang. >> >> The workaround for Errata #i2037 is to limit the maximum read >> request size and maximum payload size to 128 Bytes. Add workaround >> for Errata #i2037 here. The errata and workaround is applicable >> only to AM65x SR 1.0 and later versions of the silicon will have >> this fixed. >> >> [1] -> http://www.ti.com/lit/er/sprz452d/sprz452d.pdf >> >> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> >> Signed-off-by: Achal Verma <a-verma1@ti.com> >> Link: https://lore.kernel.org/linux-pci/20210325090026.8843-7-kishon@ti.com/ > > Please drop the above. It needs to be mentioned as the v1 below the > tear-line. > >> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> >> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> >> --- >> >> Needed for the IOT2050 PG1 variants. Pending downstream way too long. >> >> drivers/pci/controller/dwc/pci-keystone.c | 42 +++++++++++++++++++++++ >> 1 file changed, 42 insertions(+) >> >> diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c >> index d3a7d14ee685..a04f1087ce91 100644 >> --- a/drivers/pci/controller/dwc/pci-keystone.c >> +++ b/drivers/pci/controller/dwc/pci-keystone.c >> @@ -34,6 +34,11 @@ >> #define PCIE_DEVICEID_SHIFT 16 > > [...] > >> >> + static const struct pci_device_id am6_pci_devids[] = { >> + { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_AM654X), >> + .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, }, >> + { 0, }, >> + }; >> >> if (pci_is_root_bus(bus)) >> bridge = dev; >> @@ -562,6 +578,32 @@ static void ks_pcie_quirk(struct pci_dev *dev) >> pcie_set_readrq(dev, 256); >> } >> } >> + >> + /* >> + * Memory transactions fail with PCI controller in AM654 PG1.0 >> + * when MRRS is set to more than 128 Bytes. Force the MRRS to >> + * 128 Bytes in all downstream devices. >> + */ > > Comments on the v1 patch at: > https://lore.kernel.org/linux-pci/YF2K6+R1P3SNUoo5@rocinante/ > haven't been addressed in this patch. Kindly update the patch based on > Krzysztof's feedback on the v1 patch. > Oops, I didn't even realized that the link above pointed here - let me fix this up quickly. Jan >> + if (pci_match_id(am6_pci_devids, bridge)) { >> + bridge_dev = pci_get_host_bridge_device(dev); >> + if (!bridge_dev && !bridge_dev->parent) >> + return; >> + >> + ks_pcie = dev_get_drvdata(bridge_dev->parent); >> + if (!ks_pcie) >> + return; >> + >> + val = ks_pcie_app_readl(ks_pcie, PID); >> + val &= RTL; >> + val >>= RTL_SHIFT; >> + if (val != AM6_PCI_PG1_RTL_VER) >> + return; >> + >> + if (pcie_get_readrq(dev) > 128) { >> + dev_info(&dev->dev, "limiting MRRS to 128\n"); >> + pcie_set_readrq(dev, 128); >> + } >> + } >> } >> DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, ks_pcie_quirk); > > Regards, > Siddharth.
diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index d3a7d14ee685..a04f1087ce91 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -34,6 +34,11 @@ #define PCIE_DEVICEID_SHIFT 16 /* Application registers */ +#define PID 0x000 +#define RTL GENMASK(15, 11) +#define RTL_SHIFT 11 +#define AM6_PCI_PG1_RTL_VER 0x15 + #define CMD_STATUS 0x004 #define LTSSM_EN_VAL BIT(0) #define OB_XLAT_EN_VAL BIT(1) @@ -104,6 +109,8 @@ #define to_keystone_pcie(x) dev_get_drvdata((x)->dev) +#define PCI_DEVICE_ID_TI_AM654X 0xb00c + struct ks_pcie_of_data { enum dw_pcie_device_mode mode; const struct dw_pcie_host_ops *host_ops; @@ -525,7 +532,11 @@ static int ks_pcie_start_link(struct dw_pcie *pci) static void ks_pcie_quirk(struct pci_dev *dev) { struct pci_bus *bus = dev->bus; + struct keystone_pcie *ks_pcie; + struct device *bridge_dev; struct pci_dev *bridge; + u32 val; + static const struct pci_device_id rc_pci_devids[] = { { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2HK), .class = PCI_CLASS_BRIDGE_PCI_NORMAL, .class_mask = ~0, }, @@ -537,6 +548,11 @@ static void ks_pcie_quirk(struct pci_dev *dev) .class = PCI_CLASS_BRIDGE_PCI_NORMAL, .class_mask = ~0, }, { 0, }, }; + static const struct pci_device_id am6_pci_devids[] = { + { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_AM654X), + .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, }, + { 0, }, + }; if (pci_is_root_bus(bus)) bridge = dev; @@ -562,6 +578,32 @@ static void ks_pcie_quirk(struct pci_dev *dev) pcie_set_readrq(dev, 256); } } + + /* + * Memory transactions fail with PCI controller in AM654 PG1.0 + * when MRRS is set to more than 128 Bytes. Force the MRRS to + * 128 Bytes in all downstream devices. + */ + if (pci_match_id(am6_pci_devids, bridge)) { + bridge_dev = pci_get_host_bridge_device(dev); + if (!bridge_dev && !bridge_dev->parent) + return; + + ks_pcie = dev_get_drvdata(bridge_dev->parent); + if (!ks_pcie) + return; + + val = ks_pcie_app_readl(ks_pcie, PID); + val &= RTL; + val >>= RTL_SHIFT; + if (val != AM6_PCI_PG1_RTL_VER) + return; + + if (pcie_get_readrq(dev) > 128) { + dev_info(&dev->dev, "limiting MRRS to 128\n"); + pcie_set_readrq(dev, 128); + } + } } DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, ks_pcie_quirk);