Message ID | 20241025215038.3125626-8-michal.winiarski@intel.com |
---|---|
State | New |
Headers | show
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mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; Received: from DM4PR11MB5373.namprd11.prod.outlook.com (2603:10b6:5:394::7) by CY8PR11MB7745.namprd11.prod.outlook.com (2603:10b6:930:90::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8093.16; Fri, 25 Oct 2024 21:51:29 +0000 Received: from DM4PR11MB5373.namprd11.prod.outlook.com ([fe80::927a:9c08:26f7:5b39]) by DM4PR11MB5373.namprd11.prod.outlook.com ([fe80::927a:9c08:26f7:5b39%5]) with mapi id 15.20.8093.018; Fri, 25 Oct 2024 21:51:29 +0000 From: =?utf-8?q?Micha=C5=82_Winiarski?= <michal.winiarski@intel.com> To: <linux-pci@vger.kernel.org>, <intel-xe@lists.freedesktop.org>, <dri-devel@lists.freedesktop.org>, <linux-kernel@vger.kernel.org>, "Bjorn Helgaas" <bhelgaas@google.com>, =?utf-8?q?Christian_K=C3=B6nig?= <christian.koenig@amd.com>, =?utf-8?q?Krzy?= =?utf-8?q?sztof_Wilczy=C5=84ski?= <kw@linux.com>, =?utf-8?q?Ilpo_J=C3=A4rvi?= =?utf-8?q?nen?= <ilpo.jarvinen@linux.intel.com> CC: Rodrigo Vivi <rodrigo.vivi@intel.com>, Michal Wajdeczko <michal.wajdeczko@intel.com>, Lucas De Marchi <lucas.demarchi@intel.com>, =?utf-8?q?Thomas_Hellstr=C3=B6m?= <thomas.hellstrom@linux.intel.com>, Maarten Lankhorst <maarten.lankhorst@linux.intel.com>, Maxime Ripard <mripard@kernel.org>, Thomas Zimmermann <tzimmermann@suse.de>, David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>, Matt Roper <matthew.d.roper@intel.com>, =?utf-8?q?Micha=C5=82_Winiarski?= <michal.winiarski@intel.com> Subject: [PATCH v4 7/7] drm/xe/pf: Set VF LMEM BAR size Date: Fri, 25 Oct 2024 23:50:38 +0200 Message-ID: <20241025215038.3125626-8-michal.winiarski@intel.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241025215038.3125626-1-michal.winiarski@intel.com> References: <20241025215038.3125626-1-michal.winiarski@intel.com> Content-Type: text/plain; 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PCI: VF resizable BAR
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diff --git a/drivers/gpu/drm/xe/regs/xe_bars.h b/drivers/gpu/drm/xe/regs/xe_bars.h index ce05b6ae832f1..880140d6ccdca 100644 --- a/drivers/gpu/drm/xe/regs/xe_bars.h +++ b/drivers/gpu/drm/xe/regs/xe_bars.h @@ -7,5 +7,6 @@ #define GTTMMADR_BAR 0 /* MMIO + GTT */ #define LMEM_BAR 2 /* VRAM */ +#define VF_LMEM_BAR 9 /* VF VRAM */ #endif diff --git a/drivers/gpu/drm/xe/xe_pci_sriov.c b/drivers/gpu/drm/xe/xe_pci_sriov.c index aaceee748287e..57cdeb41ef1d9 100644 --- a/drivers/gpu/drm/xe/xe_pci_sriov.c +++ b/drivers/gpu/drm/xe/xe_pci_sriov.c @@ -3,6 +3,10 @@ * Copyright © 2023-2024 Intel Corporation */ +#include <linux/bitops.h> +#include <linux/pci.h> + +#include "regs/xe_bars.h" #include "xe_assert.h" #include "xe_device.h" #include "xe_gt_sriov_pf_config.h" @@ -62,6 +66,18 @@ static void pf_reset_vfs(struct xe_device *xe, unsigned int num_vfs) xe_gt_sriov_pf_control_trigger_flr(gt, n); } +static int resize_vf_vram_bar(struct xe_device *xe, int num_vfs) +{ + struct pci_dev *pdev = to_pci_dev(xe->drm.dev); + u32 sizes; + + sizes = pci_iov_vf_bar_get_sizes(pdev, VF_LMEM_BAR, num_vfs); + if (!sizes) + return 0; + + return pci_iov_vf_bar_set_size(pdev, VF_LMEM_BAR, __fls(sizes)); +} + static int pf_enable_vfs(struct xe_device *xe, int num_vfs) { struct pci_dev *pdev = to_pci_dev(xe->drm.dev); @@ -88,6 +104,12 @@ static int pf_enable_vfs(struct xe_device *xe, int num_vfs) if (err < 0) goto failed; + if (IS_DGFX(xe)) { + err = resize_vf_vram_bar(xe, num_vfs); + if (err) + xe_sriov_info(xe, "Failed to set VF LMEM BAR size: %d\n", err); + } + err = pci_enable_sriov(pdev, num_vfs); if (err < 0) goto failed;
LMEM is partitioned between multiple VFs and we expect that the more VFs we have, the less LMEM is assigned to each VF. This means that we can achieve full LMEM BAR access without the need to attempt full VF LMEM BAR resize via pci_resize_resource(). Always set the largest possible BAR size that allows to fit the number of enabled VFs. Signed-off-by: Michał Winiarski <michal.winiarski@intel.com> --- drivers/gpu/drm/xe/regs/xe_bars.h | 1 + drivers/gpu/drm/xe/xe_pci_sriov.c | 22 ++++++++++++++++++++++ 2 files changed, 23 insertions(+)