| Message ID | 20241024-pcie_ep_range-v4-4-08f8dcd4e481@nxp.com |
|---|---|
| State | New |
| Headers | show |
| Series | PCI: ep: dwc/imx6: Add bus address support for PCI endpoint devices | expand |
On Thu, Oct 24, 2024 at 04:41:46PM -0400, Frank Li wrote: > Add support for i.MX8Q series (i.MX8QM, i.MX8QXP, and i.MX8DXL) PCIe > Endpoint (EP). On i.MX8Q platforms, the PCI bus addresses differ from the > CPU addresses. The DesignWare (DWC) driver already handles this in the > common code. > > Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com> > Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > Signed-off-by: Frank Li <Frank.Li@nxp.com> > --- > Chagne from v3 to v4 > - none > change from v2 to v3 > - add Mani's review tag > - Add pci->using_dtbus_info = true; > --- > drivers/pci/controller/dwc/pci-imx6.c | 22 ++++++++++++++++++++++ > 1 file changed, 22 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c > index bdc2b372e6c13..5be9bac6206a7 100644 > --- a/drivers/pci/controller/dwc/pci-imx6.c > +++ b/drivers/pci/controller/dwc/pci-imx6.c > @@ -70,6 +70,7 @@ enum imx_pcie_variants { > IMX8MQ_EP, > IMX8MM_EP, > IMX8MP_EP, > + IMX8Q_EP, > IMX95_EP, > }; > > @@ -1079,6 +1080,16 @@ static const struct pci_epc_features imx8m_pcie_epc_features = { > .align = SZ_64K, > }; > > +static const struct pci_epc_features imx8q_pcie_epc_features = { > + .linkup_notifier = false, > + .msi_capable = true, > + .msix_capable = false, > + .bar[BAR_1] = { .type = BAR_RESERVED, }, > + .bar[BAR_3] = { .type = BAR_RESERVED, }, > + .bar[BAR_5] = { .type = BAR_RESERVED, }, > + .align = SZ_64K, > +}; > + > /* > * BAR# | Default BAR enable | Default BAR Type | Default BAR Size | BAR Sizing Scheme > * ================================================================================================ > @@ -1448,6 +1459,8 @@ static int imx_pcie_probe(struct platform_device *pdev) > if (ret) > return ret; > > + pci->using_dtbus_info = true; I mentioned this elsewhere, but I think the using_dtbus_info part should be part of a series that only deals with the address translation, and adding IMX8Q_EP should be in a separate series. > if (imx_pcie->drvdata->mode == DW_PCIE_EP_TYPE) { > ret = imx_add_pcie_ep(imx_pcie, pdev); > if (ret < 0) > @@ -1645,6 +1658,14 @@ static const struct imx_pcie_drvdata drvdata[] = { > .epc_features = &imx8m_pcie_epc_features, > .enable_ref_clk = imx8mm_pcie_enable_ref_clk, > }, > + [IMX8Q_EP] = { > + .variant = IMX8Q_EP, > + .flags = IMX_PCIE_FLAG_HAS_PHYDRV, > + .mode = DW_PCIE_EP_TYPE, > + .epc_features = &imx8q_pcie_epc_features, > + .clk_names = imx8q_clks, > + .clks_cnt = ARRAY_SIZE(imx8q_clks), > + }, > [IMX95_EP] = { > .variant = IMX95_EP, > .flags = IMX_PCIE_FLAG_HAS_SERDES | > @@ -1674,6 +1695,7 @@ static const struct of_device_id imx_pcie_of_match[] = { > { .compatible = "fsl,imx8mq-pcie-ep", .data = &drvdata[IMX8MQ_EP], }, > { .compatible = "fsl,imx8mm-pcie-ep", .data = &drvdata[IMX8MM_EP], }, > { .compatible = "fsl,imx8mp-pcie-ep", .data = &drvdata[IMX8MP_EP], }, > + { .compatible = "fsl,imx8q-pcie-ep", .data = &drvdata[IMX8Q_EP], }, > { .compatible = "fsl,imx95-pcie-ep", .data = &drvdata[IMX95_EP], }, > {}, > }; > > -- > 2.34.1 >
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index bdc2b372e6c13..5be9bac6206a7 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -70,6 +70,7 @@ enum imx_pcie_variants { IMX8MQ_EP, IMX8MM_EP, IMX8MP_EP, + IMX8Q_EP, IMX95_EP, }; @@ -1079,6 +1080,16 @@ static const struct pci_epc_features imx8m_pcie_epc_features = { .align = SZ_64K, }; +static const struct pci_epc_features imx8q_pcie_epc_features = { + .linkup_notifier = false, + .msi_capable = true, + .msix_capable = false, + .bar[BAR_1] = { .type = BAR_RESERVED, }, + .bar[BAR_3] = { .type = BAR_RESERVED, }, + .bar[BAR_5] = { .type = BAR_RESERVED, }, + .align = SZ_64K, +}; + /* * BAR# | Default BAR enable | Default BAR Type | Default BAR Size | BAR Sizing Scheme * ================================================================================================ @@ -1448,6 +1459,8 @@ static int imx_pcie_probe(struct platform_device *pdev) if (ret) return ret; + pci->using_dtbus_info = true; + if (imx_pcie->drvdata->mode == DW_PCIE_EP_TYPE) { ret = imx_add_pcie_ep(imx_pcie, pdev); if (ret < 0) @@ -1645,6 +1658,14 @@ static const struct imx_pcie_drvdata drvdata[] = { .epc_features = &imx8m_pcie_epc_features, .enable_ref_clk = imx8mm_pcie_enable_ref_clk, }, + [IMX8Q_EP] = { + .variant = IMX8Q_EP, + .flags = IMX_PCIE_FLAG_HAS_PHYDRV, + .mode = DW_PCIE_EP_TYPE, + .epc_features = &imx8q_pcie_epc_features, + .clk_names = imx8q_clks, + .clks_cnt = ARRAY_SIZE(imx8q_clks), + }, [IMX95_EP] = { .variant = IMX95_EP, .flags = IMX_PCIE_FLAG_HAS_SERDES | @@ -1674,6 +1695,7 @@ static const struct of_device_id imx_pcie_of_match[] = { { .compatible = "fsl,imx8mq-pcie-ep", .data = &drvdata[IMX8MQ_EP], }, { .compatible = "fsl,imx8mm-pcie-ep", .data = &drvdata[IMX8MM_EP], }, { .compatible = "fsl,imx8mp-pcie-ep", .data = &drvdata[IMX8MP_EP], }, + { .compatible = "fsl,imx8q-pcie-ep", .data = &drvdata[IMX8Q_EP], }, { .compatible = "fsl,imx95-pcie-ep", .data = &drvdata[IMX95_EP], }, {}, };