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Tue, 8 Oct 2024 22:19:50 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN3PEPF0000B074.mail.protection.outlook.com (10.167.243.119) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8048.13 via Frontend Transport; Tue, 8 Oct 2024 22:19:50 +0000 Received: from ethanolx7ea3host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 8 Oct 2024 17:19:49 -0500 From: Terry Bowman To: , , , , , , , , , , , , , , , , , Subject: [PATCH 15/15] cxl/pci: Enable internal CE/UCE interrupts for CXL PCIe port devices Date: Tue, 8 Oct 2024 17:16:57 -0500 Message-ID: <20241008221657.1130181-16-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241008221657.1130181-1-terry.bowman@amd.com> References: <20241008221657.1130181-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B074:EE_|SJ2PR12MB7920:EE_ X-MS-Office365-Filtering-Correlation-Id: 8607cf10-952b-4600-14af-08dce7e753a3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|7416014|1800799024|376014|921020; X-Microsoft-Antispam-Message-Info: ICJNj2fPAQfGWJ5wbJsDtJNj8g5xycv1ZPPPIzvFKJBaK9Ceu3hTHPQnxITtcM0ZXPrYSO6KdkkEPzyuCoPTCgE5BnkWzHwqx/oHvWiPYCpriWrtUXDFkb1oUdU1ufrGWAS4nZoDzaW4myY08w/5SCLyI1HFsz3xnE/OD8SKf6eRgCaaCHCjiBfxDrtz7G0bbUKAXOm45elNm0quraDEBaCBFAYQ4S1ZHs5iwqGHzLPVuITCG9DgRcQayf8yO1RI2JCeP617jv3+ddRNMlP/BGT6dwJWrVqPpEHB4N0AWzReB/lJnNsC7Veqy4naHm4KAj34tIaF346j+VpHtMMnU3Zl69whW+t3wHYlQCvwDjpslGYSceE54USiynzMu/Qo82SKr4yL0VtMmWwuXL5/cwUITCJd+YseeF0ady/LjIiBYh9tLx0Rw49pieK7uOGB432BCs3VNUiLno7t70Ca7ic2WvN8Mnnxg9ZaS1cE595EcF3W1MniFEqINhoGJlIC8WJ1ndjUShqMNwEElUhCYGapuzYdYuKl0XOmQATM0odSJ7Ep6rV75E3KSAJSwRq8lL1gDNbntZ+4IXzHp6XgCpUqFmoq0xLXSiEfAGJbfrLgxcWFCLvwx4/ARfNPyYkjn4hm0T2QxAUgRl6fpNlHxhXSqYid7uyvv41IrRJBianeyWoUq9nQ8tNn7yh1HGVyNtL+PQ3kPBwKEvuwaDu4NLQ44274GgOp/koMozekDiwkkMVbQ4c6SJ2X40xB0JXmKziEI8qcuxthOROuZUQARlME5EKqEjH7+VXako1VLB2mJ+ESNeIdvC54Sw9xmoLh2iA3RYhK8FTIvbjmlubVNpA/HaiYvcPA7nxD5S10qkb9YJtUhGK62lgLXSef9iScfc+Mqdis72FaUdFrK9v7PXKkFDDUN5GBFaKuI+dPwsg9uM3is7ii/HUSJo2wrktOLEj9zTgP6eLgPmkOrKi46oJ9DKpUPk12xj1JydfyTe9oxtPWXwgL9cvvf5GjpTYFljrfMieSqmfvo2+XjIosnDR0US19wMPvMDyjFNJpYsxqaMhRlINkQ/pTm/ROE2WcJxBe6xgBP8S8Ar+SezbNZjgU0I3AGMACt2ATUfDwjNuvxuDQ9P12I5f1vZhGj/PxFQKDIQLOmEGh1RHpijsFjJ7trsk8/Zev+y6VsfpecGFD0qs9g0tXMcTGdONXHYVyZ0EfWtcFASUvgGl4nQbbjINst4MyDWRFPw1P2ibZBO223jwPkrSDbYxhnyAf9sD1HmKqCoJR2MKXC4Ti+WLVAUJcS5EHDWHrPm90HRz7M0hVOq3GnReYaJTeUxfyVnAhpAGHHsCTlxC4dl4ZFH2kAHoJDuZ8ZIqjqsXzrudqcvt3mVQAyrtTOv3HfpEqlIDk X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(7416014)(1800799024)(376014)(921020);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2024 22:19:50.5644 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8607cf10-952b-4600-14af-08dce7e753a3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B074.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB7920 The AER service drivers and CXL drivers are updated to handle PCIe port protocol errors. But, the PCIe AER correctable and uncorrectable internal errors are mask disabled for the PCIe port devices. Enable the AER internal errors for CXL PCIe port devices. Signed-off-by: Terry Bowman Reviewed-by: Jonathan Cameron --- drivers/cxl/core/pci.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 4706113d2582..1d84a7022c4d 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -908,6 +908,7 @@ EXPORT_SYMBOL_NS_GPL(cxl_port_err_detected, CXL); void cxl_uport_init_aer(struct cxl_port *port) { + struct pci_dev *pdev = to_pci_dev(port->uport_dev); /* uport may have more than 1 downstream EP. Check if already mapped. */ if (port->uport_regs.ras) { dev_warn(&port->dev, "RAS is already mapped\n"); @@ -920,12 +921,14 @@ void cxl_uport_init_aer(struct cxl_port *port) dev_err(&port->dev, "Failed to map RAS capability.\n"); return; } + pci_aer_unmask_internal_errors(pdev); } EXPORT_SYMBOL_NS_GPL(cxl_uport_init_aer, CXL); void cxl_dport_init_aer(struct cxl_dport *dport) { struct device *dport_dev = dport->dport_dev; + struct pci_dev *pdev = to_pci_dev(dport_dev); if (dport->rch) { struct pci_host_bridge *host_bridge = to_pci_host_bridge(dport_dev); @@ -949,6 +952,7 @@ void cxl_dport_init_aer(struct cxl_dport *dport) dev_err(dport_dev, "Failed to map RAS capability.\n"); return; } + pci_aer_unmask_internal_errors(pdev); } EXPORT_SYMBOL_NS_GPL(cxl_dport_init_aer, CXL);