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Fri, 20 Sep 2024 10:18:22 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 48KAIIOt000988 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 20 Sep 2024 10:18:18 GMT Received: from hu-krichai-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 20 Sep 2024 03:18:13 -0700 From: Krishna chaitanya chundru Date: Fri, 20 Sep 2024 15:47:59 +0530 Subject: [PATCH v2 1/2] PCI: qcom: Skip wait for link up if global IRQ handler is present Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240920-remove_wait-v2-1-7c0fcb3b581d@quicinc.com> References: <20240920-remove_wait-v2-0-7c0fcb3b581d@quicinc.com> In-Reply-To: <20240920-remove_wait-v2-0-7c0fcb3b581d@quicinc.com> To: Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas CC: , , , , , , , , , Krishna chaitanya chundru X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1726827488; l=2707; i=quic_krichai@quicinc.com; s=20230907; h=from:subject:message-id; bh=Jg3kUh3LENtboxvNsh4oHW5hZseAcTacMcPUOUeoOEU=; b=d/KQfeZMOILbn0XfdkWrdeg29cVYm4vxmpr8wdx/nTSgaElg8uoa0gYT8CnZGG/Jw/2Ccxp+J 3iQSQdbqrAfCffr2F69kAWtofZW4grLlGqDouXspIDh7wWfLXEQ15NH X-Developer-Key: i=quic_krichai@quicinc.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: yGJ3MWYGEtYf0jeZ7EtyQl2Xy5-6X2Gd X-Proofpoint-GUID: yGJ3MWYGEtYf0jeZ7EtyQl2Xy5-6X2Gd X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 clxscore=1015 phishscore=0 impostorscore=0 bulkscore=0 adultscore=0 suspectscore=0 lowpriorityscore=0 malwarescore=0 spamscore=0 mlxscore=0 mlxlogscore=988 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2409200074 In cases where a global IRQ handler is present to manage link up interrupts, it may not be necessary to wait for the link to be up during PCI initialization which optimizes the bootup time. Move platform_get_irq_byname_optional() above to set linkup_irq before dw_pcie_host_init() as this flag is used in this function only. Signed-off-by: Krishna chaitanya chundru --- drivers/pci/controller/dwc/pcie-designware-host.c | 11 +++++++++-- drivers/pci/controller/dwc/pcie-designware.h | 1 + drivers/pci/controller/dwc/pcie-qcom.c | 5 ++++- 3 files changed, 14 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 3e41865c7290..b7d20a1bab0a 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -530,8 +530,15 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) goto err_remove_edma; } - /* Ignore errors, the link may come up later */ - dw_pcie_wait_for_link(pci); + /* + * Note: The link up delay is skipped only when a link up IRQ is present. + * This flag should not be used to bypass the link up delay for arbitrary + * reasons. + * + * Ignore errors, the link may come up later. + */ + if (!pp->linkup_irq) + dw_pcie_wait_for_link(pci); bridge->sysdata = pp; diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index e518f81ea80c..b850f0a74695 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -348,6 +348,7 @@ struct dw_pcie_rp { bool use_atu_msg; int msg_atu_index; struct resource *msg_res; + bool linkup_irq; }; struct dw_pcie_ep_ops { diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 88a98be930e3..905c9154fc65 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1686,6 +1686,10 @@ static int qcom_pcie_probe(struct platform_device *pdev) platform_set_drvdata(pdev, pcie); + irq = platform_get_irq_byname_optional(pdev, "global"); + if (irq > 0) + pp->linkup_irq = true; + ret = dw_pcie_host_init(pp); if (ret) { dev_err(dev, "cannot initialize host\n"); @@ -1699,7 +1703,6 @@ static int qcom_pcie_probe(struct platform_device *pdev) goto err_host_deinit; } - irq = platform_get_irq_byname_optional(pdev, "global"); if (irq > 0) { ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, qcom_pcie_global_irq_thread,