| Message ID | 20240731143946.3478057-6-matthew.gerlach@linux.intel.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add PCIe Root Port support for Agilex family of chips | expand |
On Wed, 31 Jul 2024, matthew.gerlach@linux.intel.com wrote: > From: Matthew Gerlach <matthew.gerlach@linux.intel.com> > > Add the base device tree for support of the PCIe Root Port > for the Agilex family of chips. > > Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> > --- > .../intel/socfpga_agilex_pcie_root_port.dtsi | 55 +++++++++++++++++++ > 1 file changed, 55 insertions(+) > create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex_pcie_root_port.dtsi > > diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_pcie_root_port.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex_pcie_root_port.dtsi > new file mode 100644 > index 000000000000..510dcd1c2913 > --- /dev/null > +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_pcie_root_port.dtsi > @@ -0,0 +1,55 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (C) 2024, Intel Corporation > + */ > +&soc0 { > + aglx_hps_bridges: bridge@80000000 { The node name, bridge@80000000, causing the following CHECK_DTBS error: nodename:0: 'bridge@80000000' does not match '^([a-z][a-z0-9\\-]+-bus|bus|localbus|soc|axi|ahb|apb)(@.+)?$' from schema $id: http://devicetree.org/schemas/simple-bus.yaml# I will change the node name to fpga-bus@80000000 in v2. Matthew Gerlach > + compatible = "simple-bus"; > + reg = <0x80000000 0x20200000>, > + <0xf9000000 0x00100000>; > + reg-names = "axi_h2f", "axi_h2f_lw"; > + #address-cells = <0x2>; > + #size-cells = <0x1>; > + ranges = <0x00000000 0x00000000 0x80000000 0x00040000>, > + <0x00000000 0x10000000 0x90100000 0x0ff00000>, > + <0x00000000 0x20000000 0xa0000000 0x00200000>, > + <0x00000001 0x00010000 0xf9010000 0x00008000>, > + <0x00000001 0x00018000 0xf9018000 0x00000080>, > + <0x00000001 0x00018080 0xf9018080 0x00000010>; > + > + pcie_0_pcie_aglx: pcie@200000000 { > + reg = <0x00000000 0x10000000 0x10000000>, > + <0x00000001 0x00010000 0x00008000>, > + <0x00000000 0x20000000 0x00200000>; > + reg-names = "Txs", "Cra", "Hip"; > + interrupt-parent = <&intc>; > + interrupts = <GIC_SPI 0x14 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-controller; > + #interrupt-cells = <0x1>; > + device_type = "pci"; > + bus-range = <0x0000000 0x000000ff>; > + ranges = <0x82000000 0x00000000 0x00100000 0x00000000 0x10000000 0x00000000 0x0ff00000>; > + msi-parent = <&pcie_0_msi_irq>; > + #address-cells = <0x3>; > + #size-cells = <0x2>; > + interrupt-map-mask = <0x0 0x0 0x0 0x7>; > + interrupt-map = <0x0 0x0 0x0 0x1 &pcie_0_pcie_aglx 0 0 0 0x1>, > + <0x0 0x0 0x0 0x2 &pcie_0_pcie_aglx 0 0 0 0x2>, > + <0x0 0x0 0x0 0x3 &pcie_0_pcie_aglx 0 0 0 0x3>, > + <0x0 0x0 0x0 0x4 &pcie_0_pcie_aglx 0 0 0 0x4>; > + status = "disabled"; > + }; > + > + pcie_0_msi_irq: msi@10008080 { > + compatible = "altr,msi-1.0"; > + reg = <0x00000001 0x00018080 0x00000010>, > + <0x00000001 0x00018000 0x00000080>; > + reg-names = "csr", "vector_slave"; > + interrupt-parent = <&intc>; > + interrupts = <GIC_SPI 0x13 IRQ_TYPE_LEVEL_HIGH>; > + msi-controller; > + num-vectors = <0x20>; > + status = "disabled"; > + }; > + }; > +}; > -- > 2.34.1 > >
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_pcie_root_port.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex_pcie_root_port.dtsi new file mode 100644 index 000000000000..510dcd1c2913 --- /dev/null +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_pcie_root_port.dtsi @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024, Intel Corporation + */ +&soc0 { + aglx_hps_bridges: bridge@80000000 { + compatible = "simple-bus"; + reg = <0x80000000 0x20200000>, + <0xf9000000 0x00100000>; + reg-names = "axi_h2f", "axi_h2f_lw"; + #address-cells = <0x2>; + #size-cells = <0x1>; + ranges = <0x00000000 0x00000000 0x80000000 0x00040000>, + <0x00000000 0x10000000 0x90100000 0x0ff00000>, + <0x00000000 0x20000000 0xa0000000 0x00200000>, + <0x00000001 0x00010000 0xf9010000 0x00008000>, + <0x00000001 0x00018000 0xf9018000 0x00000080>, + <0x00000001 0x00018080 0xf9018080 0x00000010>; + + pcie_0_pcie_aglx: pcie@200000000 { + reg = <0x00000000 0x10000000 0x10000000>, + <0x00000001 0x00010000 0x00008000>, + <0x00000000 0x20000000 0x00200000>; + reg-names = "Txs", "Cra", "Hip"; + interrupt-parent = <&intc>; + interrupts = <GIC_SPI 0x14 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <0x1>; + device_type = "pci"; + bus-range = <0x0000000 0x000000ff>; + ranges = <0x82000000 0x00000000 0x00100000 0x00000000 0x10000000 0x00000000 0x0ff00000>; + msi-parent = <&pcie_0_msi_irq>; + #address-cells = <0x3>; + #size-cells = <0x2>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &pcie_0_pcie_aglx 0 0 0 0x1>, + <0x0 0x0 0x0 0x2 &pcie_0_pcie_aglx 0 0 0 0x2>, + <0x0 0x0 0x0 0x3 &pcie_0_pcie_aglx 0 0 0 0x3>, + <0x0 0x0 0x0 0x4 &pcie_0_pcie_aglx 0 0 0 0x4>; + status = "disabled"; + }; + + pcie_0_msi_irq: msi@10008080 { + compatible = "altr,msi-1.0"; + reg = <0x00000001 0x00018080 0x00000010>, + <0x00000001 0x00018000 0x00000080>; + reg-names = "csr", "vector_slave"; + interrupt-parent = <&intc>; + interrupts = <GIC_SPI 0x13 IRQ_TYPE_LEVEL_HIGH>; + msi-controller; + num-vectors = <0x20>; + status = "disabled"; + }; + }; +};