| Message ID | 20240716092347.2177153-5-quic_srichara@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add PCIe support for IPQ9574 | expand |
On Tue, Jul 16, 2024 at 02:53:47PM +0530, Sricharan R wrote: > From: devi priya <quic_devipriy@quicinc.com> > > The IPQ9574 platform has four Gen3 PCIe controllers: > two single-lane and two dual-lane based on SNPS core 5.70a. > > QCOM IP rev is 1.27.0 and Synopsys IP rev is 5.80a. > Add a new compatible 'qcom,pcie-ipq9574' and 'ops_1_27_0' > which reuses all the members of 'ops_2_9_0' except for the > post_init as the SLV_ADDR_SPACE_SIZE configuration differs > between 2_9_0 and 1_27_0. > > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > Reviewed-by: Manivannan Sadhasivam <mani@kernel.org> > Co-developed-by: Anusha Rao <quic_anusha@quicinc.com> > Signed-off-by: Anusha Rao <quic_anusha@quicinc.com> > Signed-off-by: devi priya <quic_devipriy@quicinc.com> > Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> > --- > [V6] Fixed all Manivannan's and Bjorn Helgaas comments. > Removed the SLV_ADDR_SPACE_SZ_1_27_0 macro to have default value. > > drivers/pci/controller/dwc/pcie-qcom.c | 31 ++++++++++++++++++++++---- > 1 file changed, 27 insertions(+), 4 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index 0180edf3310e..26acd9f5385e 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -1116,16 +1116,13 @@ static int qcom_pcie_init_2_9_0(struct qcom_pcie *pcie) > return clk_bulk_prepare_enable(res->num_clks, res->clks); > } > > -static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie) > +static int qcom_pcie_post_init(struct qcom_pcie *pcie) > { > struct dw_pcie *pci = pcie->pci; > u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); > u32 val; > int i; > > - writel(SLV_ADDR_SPACE_SZ, > - pcie->parf + PARF_SLV_ADDR_SPACE_SIZE); > - > val = readl(pcie->parf + PARF_PHY_CTRL); > val &= ~PHY_TEST_PWR_DOWN; > writel(val, pcie->parf + PARF_PHY_CTRL); > @@ -1165,6 +1162,18 @@ static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie) > return 0; > } > > +static int qcom_pcie_post_init_1_27_0(struct qcom_pcie *pcie) > +{ > + return qcom_pcie_post_init(pcie); > +} > + > +static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie) > +{ > + writel(SLV_ADDR_SPACE_SZ, pcie->parf + PARF_SLV_ADDR_SPACE_SIZE); > + As discussed in [1], DBI/ATU mirroring should be disabled completely to avoid the enumeration issue you are seeing on this platform. Please rebase on top of the referenced patch (once v2 gets posted). - Mani [1] https://lore.kernel.org/linux-arm-msm/a01404d2-2f4d-4fb8-af9d-3db66d39acf7@quicinc.com/
On 7/17/2024 2:08 PM, Manivannan Sadhasivam wrote: > On Tue, Jul 16, 2024 at 02:53:47PM +0530, Sricharan R wrote: >> From: devi priya <quic_devipriy@quicinc.com> >> >> The IPQ9574 platform has four Gen3 PCIe controllers: >> two single-lane and two dual-lane based on SNPS core 5.70a. >> >> QCOM IP rev is 1.27.0 and Synopsys IP rev is 5.80a. >> Add a new compatible 'qcom,pcie-ipq9574' and 'ops_1_27_0' >> which reuses all the members of 'ops_2_9_0' except for the >> post_init as the SLV_ADDR_SPACE_SIZE configuration differs >> between 2_9_0 and 1_27_0. >> >> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> >> Reviewed-by: Manivannan Sadhasivam <mani@kernel.org> >> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com> >> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com> >> Signed-off-by: devi priya <quic_devipriy@quicinc.com> >> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> >> --- >> [V6] Fixed all Manivannan's and Bjorn Helgaas comments. >> Removed the SLV_ADDR_SPACE_SZ_1_27_0 macro to have default value. >> >> drivers/pci/controller/dwc/pcie-qcom.c | 31 ++++++++++++++++++++++---- >> 1 file changed, 27 insertions(+), 4 deletions(-) >> >> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c >> index 0180edf3310e..26acd9f5385e 100644 >> --- a/drivers/pci/controller/dwc/pcie-qcom.c >> +++ b/drivers/pci/controller/dwc/pcie-qcom.c >> @@ -1116,16 +1116,13 @@ static int qcom_pcie_init_2_9_0(struct qcom_pcie *pcie) >> return clk_bulk_prepare_enable(res->num_clks, res->clks); >> } >> >> -static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie) >> +static int qcom_pcie_post_init(struct qcom_pcie *pcie) >> { >> struct dw_pcie *pci = pcie->pci; >> u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); >> u32 val; >> int i; >> >> - writel(SLV_ADDR_SPACE_SZ, >> - pcie->parf + PARF_SLV_ADDR_SPACE_SIZE); >> - >> val = readl(pcie->parf + PARF_PHY_CTRL); >> val &= ~PHY_TEST_PWR_DOWN; >> writel(val, pcie->parf + PARF_PHY_CTRL); >> @@ -1165,6 +1162,18 @@ static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie) >> return 0; >> } >> >> +static int qcom_pcie_post_init_1_27_0(struct qcom_pcie *pcie) >> +{ >> + return qcom_pcie_post_init(pcie); >> +} >> + >> +static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie) >> +{ >> + writel(SLV_ADDR_SPACE_SZ, pcie->parf + PARF_SLV_ADDR_SPACE_SIZE); >> + > As discussed in [1], DBI/ATU mirroring should be disabled completely to avoid > the enumeration issue you are seeing on this platform. Please rebase on top of > the referenced patch (once v2 gets posted). ok, got it. Regards, Sricharan
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 0180edf3310e..26acd9f5385e 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1116,16 +1116,13 @@ static int qcom_pcie_init_2_9_0(struct qcom_pcie *pcie) return clk_bulk_prepare_enable(res->num_clks, res->clks); } -static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie) +static int qcom_pcie_post_init(struct qcom_pcie *pcie) { struct dw_pcie *pci = pcie->pci; u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); u32 val; int i; - writel(SLV_ADDR_SPACE_SZ, - pcie->parf + PARF_SLV_ADDR_SPACE_SIZE); - val = readl(pcie->parf + PARF_PHY_CTRL); val &= ~PHY_TEST_PWR_DOWN; writel(val, pcie->parf + PARF_PHY_CTRL); @@ -1165,6 +1162,18 @@ static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie) return 0; } +static int qcom_pcie_post_init_1_27_0(struct qcom_pcie *pcie) +{ + return qcom_pcie_post_init(pcie); +} + +static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie) +{ + writel(SLV_ADDR_SPACE_SZ, pcie->parf + PARF_SLV_ADDR_SPACE_SIZE); + + return qcom_pcie_post_init(pcie); +} + static int qcom_pcie_link_up(struct dw_pcie *pci) { u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); @@ -1318,6 +1327,15 @@ static const struct qcom_pcie_ops ops_2_9_0 = { .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, }; +/* Qcom IP rev.: 1.27.0 Synopsys IP rev.: 5.80a */ +static const struct qcom_pcie_ops ops_1_27_0 = { + .get_resources = qcom_pcie_get_resources_2_9_0, + .init = qcom_pcie_init_2_9_0, + .post_init = qcom_pcie_post_init_1_27_0, + .deinit = qcom_pcie_deinit_2_9_0, + .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, +}; + static const struct qcom_pcie_cfg cfg_1_0_0 = { .ops = &ops_1_0_0, }; @@ -1360,6 +1378,10 @@ static const struct qcom_pcie_cfg cfg_sc8280xp = { .no_l0s = true, }; +static const struct qcom_pcie_cfg cfg_1_27_0 = { + .ops = &ops_1_27_0, +}; + static const struct dw_pcie_ops dw_pcie_ops = { .link_up = qcom_pcie_link_up, .start_link = qcom_pcie_start_link, @@ -1724,6 +1746,7 @@ static const struct of_device_id qcom_pcie_match[] = { { .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 }, { .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 }, { .compatible = "qcom,pcie-ipq8074-gen3", .data = &cfg_2_9_0 }, + { .compatible = "qcom,pcie-ipq9574", .data = &cfg_1_27_0 }, { .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 }, { .compatible = "qcom,pcie-qcs404", .data = &cfg_2_4_0 }, { .compatible = "qcom,pcie-sa8540p", .data = &cfg_sc8280xp },