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Thu, 9 May 2024 16:27:59 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CH3PEPF00000015.mail.protection.outlook.com (10.167.244.120) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7587.0 via Frontend Transport; Thu, 9 May 2024 16:27:59 +0000 Received: from weiserver.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 9 May 2024 11:27:58 -0500 From: Wei Huang To: , , , CC: , , , , , , , , , , , , Subject: [PATCH V1 1/9] PCI: Introduce PCIe TPH support framework Date: Thu, 9 May 2024 11:27:33 -0500 Message-ID: <20240509162741.1937586-2-wei.huang2@amd.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240509162741.1937586-1-wei.huang2@amd.com> References: <20240509162741.1937586-1-wei.huang2@amd.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF00000015:EE_|SJ2PR12MB8942:EE_ X-MS-Office365-Filtering-Correlation-Id: 936867e5-f695-4e79-cba0-08dc7044fd86 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|36860700004|82310400017|376005|7416005|1800799015; X-Microsoft-Antispam-Message-Info: 8as+7yQaeS1OJbuzcJCiukKZdJ8GTk+6Rt8JXDOV2J7kjKRB6Thke3Rkv2qz6I7NRpy4D2f59L2EDUQ3MwJDAzaSTQBMpbBGSUEX7r43Kyd/WHkCmYBdBvJjZimc783noHljZeasgGN7Ofl2hPt/MfyucTZ8xrC3AlipFTGYAh1upXUPh2/CI06h7/lWiZezT/YuNsgZvcEpVIsrXbPwPNxt7dfqlspwATENPpNc74Oa/RIacGr5eaf+DuSc+ZzDkIdhYZynQ4dKoI/4WdkG3FR5mV6EXEtwA8bwMUM8fNvdXo1YRkDZ01vXIsmh44fn81Ytj0nhEMQZwbFRfipGkrGWnMN/oQcGfgBuIQ/0u1KMyQx05oZJtq5ULvyTrIEsuALOmNZePhc/v07bP6Xt02Z9F10MLZTvRS0AQ3n9myWF+pzcqW9KhziNT8hmG9JjhvE5yLIqGlcpCwZInZ9zNPF9//0iw3PBcsYh7G/m+3u4knRbHMPseJYpEaadRKq72t7zLG9h1g/iioTokEw96pDlFpzAjqrlfq27Sa35gsLqfTHsceUOkAp5R4HGuljJAE71IElivSG0gZtYLhEBVfEowUBRrDg/TSIixnq/uThuFuOK2DluPXSbcWX5jqHP4oeKHX0GyB0bcvx3UgFqf1dO9+ifLgy6uGEDgy08XL+RZr4YWscMPFD+nbaUhYlZd14RWuJw3Vfz3oEvo6CjNd9p3NnAy8RnJ2lYiA2UTqP9jB7AjsFZSkR/KHHo9euGsjof1JakFG0R/RPxZFD8sf0saismE1c2Y8IceLmLz2IWu4mXOhzFNXjfd7B5+5+11ThzFHcUPD+JzjqciWRHDq47HqptvXwyGIWgxWi7J68eEPZbKuWS+k911+fnTemKmcvvdRvdCgE3SlqMgIvD1xMCblZtazj/VZSrSFIGB5AwrVS4hnsP336MoUIkICxo0MRhVvvnPPbpn3Ukej7e3mVrpPEiKiF6gKU/5udm5t7nZ5ifKVciIyIr0T+HpOin1AOPoiuoUOxd867NAfMAOeBoDyXeEynidWyRyBEQjrx3qZhlDAU9k9srIQdIvDOgIAQXO1BH60UxXrYCIyQnqyqMTJxPIwfp1UTRxYfNnrvcadCv662zXG+qhlqUgKQBpdlStRR4KgcxG0PRgavEwKvMbvBaCPUWGzDy/C3hkOtsuDEl1AdnNtlgtAWZhu2993BK8bSg3XjxAd1pXKbxgMJrfnpKJuM30AibRD5hTPB74d2Jlnn64jC3MXZ1KT43tAN0f0zHxlRHn+QrvE9u9UWxIF3jopEmHJ9BXv72jmQFbQ66E1j/q/Cr+BxUC/uI0QZyXCVHwXLYx3FY+0rxoCFWYEmArsBUQ5qoGMO2HmmDQaBjLzJ4ESOuo3F0qqg0 X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(36860700004)(82310400017)(376005)(7416005)(1800799015);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 May 2024 16:27:59.2699 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 936867e5-f695-4e79-cba0-08dc7044fd86 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF00000015.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8942 This patch implements the framework for PCIe TPH support. It introduces tph.c source file, along with CONFIG_PCIE_TPH, to Linux PCIe subsystem. A new member, named tph_cap, is also introduced in pci_dev to cache TPH capability offset. Co-developed-by: Eric Van Tassell Signed-off-by: Eric Van Tassell Signed-off-by: Wei Huang --- drivers/pci/pci.h | 6 ++++++ drivers/pci/pcie/Kconfig | 10 ++++++++++ drivers/pci/pcie/Makefile | 1 + drivers/pci/pcie/tph.c | 28 ++++++++++++++++++++++++++++ drivers/pci/probe.c | 1 + include/linux/pci.h | 4 ++++ 6 files changed, 50 insertions(+) create mode 100644 drivers/pci/pcie/tph.c diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 17fed1846847..6f1d35a68126 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -508,6 +508,12 @@ static inline int pci_iov_bus_range(struct pci_bus *bus) #endif /* CONFIG_PCI_IOV */ +#ifdef CONFIG_PCIE_TPH +void pcie_tph_init(struct pci_dev *dev); +#else +static inline void pcie_tph_init(struct pci_dev *dev) {} +#endif + #ifdef CONFIG_PCIE_PTM void pci_ptm_init(struct pci_dev *dev); void pci_save_ptm_state(struct pci_dev *dev); diff --git a/drivers/pci/pcie/Kconfig b/drivers/pci/pcie/Kconfig index 8999fcebde6a..a4940e2af9b1 100644 --- a/drivers/pci/pcie/Kconfig +++ b/drivers/pci/pcie/Kconfig @@ -155,3 +155,13 @@ config PCIE_EDR the PCI Firmware Specification r3.2. Enable this if you want to support hybrid DPC model which uses both firmware and OS to implement DPC. + +config PCIE_TPH + bool "TLP Processing Hints" + default n + help + This option adds support for PCIE TLP Processing Hints (TPH). + TPH allows endpoint devices to provide optimization hints, such as + desired caching behavior, for requests that target memory space. + These hints, called steering tags, can empower the system hardware + to optimize the utilization of platform resources. diff --git a/drivers/pci/pcie/Makefile b/drivers/pci/pcie/Makefile index 6461aa93fe76..3542b42ea0b9 100644 --- a/drivers/pci/pcie/Makefile +++ b/drivers/pci/pcie/Makefile @@ -13,3 +13,4 @@ obj-$(CONFIG_PCIE_PME) += pme.o obj-$(CONFIG_PCIE_DPC) += dpc.o obj-$(CONFIG_PCIE_PTM) += ptm.o obj-$(CONFIG_PCIE_EDR) += edr.o +obj-$(CONFIG_PCIE_TPH) += tph.o diff --git a/drivers/pci/pcie/tph.c b/drivers/pci/pcie/tph.c new file mode 100644 index 000000000000..5f0cc06b74bb --- /dev/null +++ b/drivers/pci/pcie/tph.c @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * TPH (TLP Processing Hints) support + * + * Copyright (C) 2024 Advanced Micro Devices, Inc. + * Eric Van Tassell + * Wei Huang + */ + +#define pr_fmt(fmt) "TPH: " fmt +#define dev_fmt pr_fmt + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../pci.h" + +void pcie_tph_init(struct pci_dev *dev) +{ + dev->tph_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_TPH); +} + diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 1325fbae2f28..9ac511032639 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -2481,6 +2481,7 @@ static void pci_init_capabilities(struct pci_dev *dev) pci_dpc_init(dev); /* Downstream Port Containment */ pci_rcec_init(dev); /* Root Complex Event Collector */ pci_doe_init(dev); /* Data Object Exchange */ + pcie_tph_init(dev); /* TLP Processing Hints */ pcie_report_downtraining(dev); pci_init_reset_methods(dev); diff --git a/include/linux/pci.h b/include/linux/pci.h index 16493426a04f..73d92c7d2c5b 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -529,6 +529,10 @@ struct pci_dev { /* These methods index pci_reset_fn_methods[] */ u8 reset_methods[PCI_NUM_RESET_METHODS]; /* In priority order */ + +#ifdef CONFIG_PCIE_TPH + u16 tph_cap; /* TPH capability offset */ +#endif }; static inline struct pci_dev *pci_physfn(struct pci_dev *dev)