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Wed, 03 Apr 2024 14:39:09 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , Cyril Brulebois , Phil Elwell , bcm-kernel-feedback-list@broadcom.com, james.quinlan@broadcom.com Cc: Florian Fainelli , Jim Quinlan , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v9 2/4] PCI: brcmstb: Set reasonable value for internal bus timeout Date: Wed, 3 Apr 2024 17:38:59 -0400 Message-Id: <20240403213902.26391-3-james.quinlan@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240403213902.26391-1-james.quinlan@broadcom.com> References: <20240403213902.26391-1-james.quinlan@broadcom.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: HW initializes an internal bus timeout register to a small value for debugging convenience. Set this to something reasonable, i.e. in the vicinity of 10 msec. Signed-off-by: Jim Quinlan --- drivers/pci/controller/pcie-brcmstb.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c index f9dd6622fe10..e3480ca4cd57 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -664,6 +664,21 @@ static int brcm_pcie_enable_msi(struct brcm_pcie *pcie) return 0; } +/* + * An internal HW bus timer value is set to a small value for debugging + * convenience. Set this to something reasonable, i.e. somewhere around + * 10ms. + */ +static void brcm_extend_internal_bus_timeout(struct brcm_pcie *pcie, u32 nsec) +{ + /* TIMEOUT register is two registers before RGR1_SW_INIT_1 */ + const unsigned int REG_OFFSET = PCIE_RGR1_SW_INIT_1(pcie) - 8; + u32 timeout_us = nsec / 1000; + + /* Each unit in timeout register is 1/216,000,000 seconds */ + writel(216 * timeout_us, pcie->base + REG_OFFSET); +} + /* The controller is capable of serving in both RC and EP roles */ static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie) { @@ -1059,6 +1074,9 @@ static int brcm_pcie_start_link(struct brcm_pcie *pcie) return -ENODEV; } + /* Extend internal bus timeout to 8ms or so */ + brcm_extend_internal_bus_timeout(pcie, SZ_8M); + if (pcie->gen) brcm_pcie_set_gen(pcie, pcie->gen);