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AJvYcCWE1jg5D4Q08mRtPkrwIAlKIor83cVkpbALTMa43LCtTq3h09wgMmlQppTtehC5mVHdTfoRjajSqUDFO3l7VysvMOAb8TDy8tnDkgAyUYLl9IQ4+Z2p+ZUykNiBPvN+VXDkR20+BLcfc8S9yno8XmxfH/irG5gL2UpjRGIYkezNbquPLz6I/9AbJWzwlz1GKOoFkKkf2exEBXet2N5+gzaKfYAvlYqF0suoH/R0sQuC65HypSYRp/f+dNvfQD53qsatkmd+XSJ1xOtWFzrIF3WxnW0tZxm98zerq1QnH0lMlstslyZ4FlLEBsqeSybwzlvuZO7yBdBcdl216aSuEwLJMkr0JcTbPYdpNHbyoJQlb2EFa8/7UEc= Received: from starnight.endlessm-sf.com ([123.51.167.56]) by smtp.googlemail.com with ESMTPSA id ff15-20020a056a002f4f00b006e04efcfbc2sm1232068pfb.74.2024.02.07.03.06.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Feb 2024 03:06:02 -0800 (PST) From: Jian-Hong Pan To: Bjorn Helgaas , Johan Hovold , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , David Box Cc: Mika Westerberg , Nirmal Patel , Jonathan Derrick , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux@endlessos.org, Jian-Hong Pan Subject: [PATCH v3 1/3] PCI: vmd: Enable PCI PM's L1 substates of remapped PCIe Root Port and NVMe Date: Wed, 7 Feb 2024 19:02:29 +0800 Message-ID: <20240207110227.575983-3-jhp@endlessos.org> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The remapped PCIe Root Port and NVMe have PCI PM L1 substates capability, but they are disabled originally. Here is a failed example on ASUS B1400CEAE: Capabilities: [900 v1] L1 PM Substates L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1- ASPM_L1.2+ ASPM_L1.1- L1_PM_Substates+ PortCommonModeRestoreTime=32us PortTPowerOnTime=10us L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2+ ASPM_L1.1- T_CommonMode=0us LTR1.2_Threshold=0ns L1SubCtl2: T_PwrOn=10us Power on all of the VMD remapped PCI devices before enable PCI-PM L1 PM Substates by following PCI Express Base Specification Revision 6.0, section 5.5.4. Link: https://bugzilla.kernel.org/show_bug.cgi?id=218394 Signed-off-by: Jian-Hong Pan --- drivers/pci/controller/vmd.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/vmd.c b/drivers/pci/controller/vmd.c index 87b7856f375a..6aca3f77724c 100644 --- a/drivers/pci/controller/vmd.c +++ b/drivers/pci/controller/vmd.c @@ -751,11 +751,9 @@ static int vmd_pm_enable_quirk(struct pci_dev *pdev, void *userdata) if (!(features & VMD_FEAT_BIOS_PM_QUIRK)) return 0; - pci_enable_link_state_locked(pdev, PCIE_LINK_STATE_ALL); - pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_LTR); if (!pos) - return 0; + goto out_enable_link_state; /* * Skip if the max snoop LTR is non-zero, indicating BIOS has set it @@ -763,7 +761,7 @@ static int vmd_pm_enable_quirk(struct pci_dev *pdev, void *userdata) */ pci_read_config_dword(pdev, pos + PCI_LTR_MAX_SNOOP_LAT, <r_reg); if (!!(ltr_reg & (PCI_LTR_VALUE_MASK | PCI_LTR_SCALE_MASK))) - return 0; + goto out_enable_link_state; /* * Set the default values to the maximum required by the platform to @@ -775,6 +773,13 @@ static int vmd_pm_enable_quirk(struct pci_dev *pdev, void *userdata) pci_write_config_dword(pdev, pos + PCI_LTR_MAX_SNOOP_LAT, ltr_reg); pci_info(pdev, "VMD: Default LTR value set by driver\n"); +out_enable_link_state: + /* + * Ensure devices are in D0 before enabling PCI-PM L1 PM Substates, per + * PCIe r6.0, sec 5.5.4. + */ + pci_set_power_state_locked(pdev, PCI_D0); + pci_enable_link_state_locked(pdev, PCIE_LINK_STATE_ALL); return 0; }