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Mon, 29 Jan 2024 06:41:34 -0800 (PST) From: Abel Vesa Date: Mon, 29 Jan 2024 16:41:19 +0200 Subject: [PATCH RESEND v2 1/2] dt-bindings: PCI: qcom: Document the X1E80100 PCIe Controller Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240129-x1e80100-pci-v2-1-5751ab805483@linaro.org> References: <20240129-x1e80100-pci-v2-0-5751ab805483@linaro.org> In-Reply-To: <20240129-x1e80100-pci-v2-0-5751ab805483@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Abel Vesa X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=2268; i=abel.vesa@linaro.org; h=from:subject:message-id; bh=sa4E+CoKAN/LlXCOMcKVwg7cxW2KNFDdu3uPIropwl8=; b=owEBbQKS/ZANAwAKARtfRMkAlRVWAcsmYgBlt7ka48SqgS4xk7S2zDXO3oXieCPjvGn4bjT45 HDu25tYG9eJAjMEAAEKAB0WIQRO8+4RTnqPKsqn0bgbX0TJAJUVVgUCZbe5GgAKCRAbX0TJAJUV VultEADD+48uozfRL2li4h3LKm7wDAMxW/hBhYZGu8MgWA1mz2dRVyR6p6NtHIPYgkIzHibfjeg zL4OB/9jPIZvp4qraLqJLpBd356jW4Gc2BCkjZViFLrZWAE+l0vTClb0nPg6toN/PfWm9i9huIx lIIoxemclkwiC5CBHv2dDlwrH4U5DOK6lrhTsS/9RWO6/7uTVfSQY3d8SyVjQfXx84Ik7qrxclq 6oPdbRTCQ/F0tV7IpWIXTgZwfCXqX+pcafWGv42Zb79TMmpioczzlIjPZsnSN3ClaVvoPHIc+tl xb7IugiJRpszWREfnXr6ImghMZMTtQ7QfqaFRkA8Mpmhxykut/Hk+WhIaw+Z8fxw25KR7eJJ/0w PW9aENi1zN82MXRjEavtHHKpzrO4qkeA6ddE4y7UO6ohTNsSVPl7S/mTwQityy+Z/VzJ6YriJdE 876DjWARvG60k3rt+0TX/z1XAC0eoWvK3R62QBiFfXrwLAL/yOEa8QbEtDzF/2KR3e5GrNr5QTe gAZQ2qhBJexc+xjLmuDWEh9m2uVn7ve7xNCP0vv3ZZAipD8Y45Cc1gF7TgrWahGJO7V28y5xX3W re73Au7FFHBkG7V5My6HvXLXkgTBj3feDMPfDNsrcGtifn/MM2FxpFYTaWs97Ee4ophO91czBzn 7th+iMjsbhXnSmg== X-Developer-Key: i=abel.vesa@linaro.org; a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE Document the PCIe Controllers on the X1E80100 platform. They are similar to the ones found on SM8550, but they don't have SF QTB clock. Signed-off-by: Abel Vesa Acked-by: Manivannan Sadhasivam Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/pci/qcom,pcie.yaml | 29 ++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index a93ab3b54066..7381e38b7398 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -41,6 +41,7 @@ properties: - qcom,pcie-sm8450-pcie0 - qcom,pcie-sm8450-pcie1 - qcom,pcie-sm8550 + - qcom,pcie-x1e80100 - items: - enum: - qcom,pcie-sm8650 @@ -227,6 +228,7 @@ allOf: - qcom,pcie-sm8450-pcie0 - qcom,pcie-sm8450-pcie1 - qcom,pcie-sm8550 + - qcom,pcie-x1e80100 then: properties: reg: @@ -826,6 +828,32 @@ allOf: items: - const: pci # PCIe core reset + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-x1e80100 + then: + properties: + clocks: + maxItems: 7 + clock-names: + items: + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: noc_aggr # Aggre NoC PCIe AXI clock + - const: cnoc_sf_axi # Config NoC PCIe1 AXI clock + resets: + maxItems: 2 + reset-names: + items: + - const: pci # PCIe core reset + - const: link_down # PCIe link down reset + - if: properties: compatible: @@ -884,6 +912,7 @@ allOf: - qcom,pcie-sm8450-pcie0 - qcom,pcie-sm8450-pcie1 - qcom,pcie-sm8550 + - qcom,pcie-x1e80100 then: oneOf: - properties: