Message ID | 20231016051102.1180432-3-thippeswamy.havalige@amd.com |
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State | New |
Headers | show
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Mon, 16 Oct 2023 00:11:39 -0500 Received: from SATLEXMB03.amd.com (10.181.40.144) by SATLEXMB08.amd.com (10.181.40.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Sun, 15 Oct 2023 22:11:38 -0700 Received: from xhdthippesw40.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2507.27 via Frontend Transport; Mon, 16 Oct 2023 00:11:35 -0500 From: Thippeswamy Havalige <thippeswamy.havalige@amd.com> To: <linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org> CC: <bhelgaas@google.com>, <lpieralisi@kernel.org>, <kw@linux.com>, <robh@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>, <colnor+dt@kernel.org>, <thippeswamy.havalige@amd.com>, <michal.simek@amd.com>, <bharat.kumar.gogada@amd.com> Subject: [PATCH v5 RESEND 2/4] dt-bindings: PCI: xilinx-nwl: Modify ECAM size in example Date: Mon, 16 Oct 2023 10:41:00 +0530 Message-ID: <20231016051102.1180432-3-thippeswamy.havalige@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231016051102.1180432-1-thippeswamy.havalige@amd.com> References: <20231016051102.1180432-1-thippeswamy.havalige@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000971E7:EE_|LV2PR12MB5822:EE_ X-MS-Office365-Filtering-Correlation-Id: 59bbbbd7-e4d2-478b-14a8-08dbce066199 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Series |
increase ecam size value to discover 256 buses during
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expand
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diff --git a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml index 897602559b37..426f90a47f35 100644 --- a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml @@ -118,7 +118,7 @@ examples: compatible = "xlnx,nwl-pcie-2.11"; reg = <0x0 0xfd0e0000 0x0 0x1000>, <0x0 0xfd480000 0x0 0x1000>, - <0x80 0x00000000 0x0 0x1000000>; + <0x80 0x00000000 0x0 0x10000000>; reg-names = "breg", "pcireg", "cfg"; ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>, <0x43000000 0x00000006 0x0 0x00000006 0x0 0x00000002 0x0>;