Message ID | 20231005164051.984254-5-thippeswamy.havalige@amd.com |
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State | New |
Headers | show
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Thu, 5 Oct 2023 11:42:07 -0500 Received: from SATLEXMB03.amd.com (10.181.40.144) by SATLEXMB08.amd.com (10.181.40.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 5 Oct 2023 09:42:06 -0700 Received: from xhdthippesw40.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2507.27 via Frontend Transport; Thu, 5 Oct 2023 11:42:03 -0500 From: Thippeswamy Havalige <thippeswamy.havalige@amd.com> To: <linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org> CC: <lpieralisi@kernel.org>, <kw@linux.com>, <robh@kernel.org>, <bhelgaas@google.com>, <krzysztof.kozlowski+dt@linaro.org>, <conor+dt@kernel.org>, <michal.simek@amd.com>, <bharat.kumar.gogada@amd.com>, Thippeswamy Havalige <thippeswamy.havalige@amd.com> Subject: [PATCH v5 RESEND 4/4] PCI: xilinx-nwl: Increase ECAM size to accommodate 256 buses Date: Thu, 5 Oct 2023 22:10:51 +0530 Message-ID: <20231005164051.984254-5-thippeswamy.havalige@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231005164051.984254-1-thippeswamy.havalige@amd.com> References: <20231005164051.984254-1-thippeswamy.havalige@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D5:EE_|IA1PR12MB7566:EE_ X-MS-Office365-Filtering-Correlation-Id: 0c90cb71-aaed-4b09-56b7-08dbc5c203cf X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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ncrease ecam size value to discover 256 buses during
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expand
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diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c index 8fe0e8a325b0..e307aceba5c9 100644 --- a/drivers/pci/controller/pcie-xilinx-nwl.c +++ b/drivers/pci/controller/pcie-xilinx-nwl.c @@ -126,7 +126,7 @@ #define E_ECAM_CR_ENABLE BIT(0) #define E_ECAM_SIZE_LOC GENMASK(20, 16) #define E_ECAM_SIZE_SHIFT 16 -#define NWL_ECAM_MAX_SIZE 12 +#define NWL_ECAM_MAX_SIZE 16 #define CFG_DMA_REG_BAR GENMASK(2, 0) #define CFG_PCIE_CACHE GENMASK(7, 0)
Our controller is expecting ECAM size to be programmed by software. By programming "NWL_ECAM_VALUE_DEFAULT 12" controller can access up to 16MB ECAM region which is used to detect 16 buses, so by updating "NWL_ECAM_VALUE_DEFAULT" to 16 so that controller can access up to 256MB ECAM region to detect 256 buses. Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com> --- changes in v5: None. --- drivers/pci/controller/pcie-xilinx-nwl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)