From patchwork Fri Jun 23 14:40:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Quinlan X-Patchwork-Id: 1799050 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=broadcom.com header.i=@broadcom.com header.a=rsa-sha256 header.s=google header.b=I+viCJg2; dkim-atps=neutral Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4Qng0h5knwz20Xk for ; Sat, 24 Jun 2023 00:41:24 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231864AbjFWOlX (ORCPT ); Fri, 23 Jun 2023 10:41:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37786 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231880AbjFWOlU (ORCPT ); Fri, 23 Jun 2023 10:41:20 -0400 Received: from mail-qk1-x733.google.com (mail-qk1-x733.google.com [IPv6:2607:f8b0:4864:20::733]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6DB8B19BF for ; Fri, 23 Jun 2023 07:41:12 -0700 (PDT) Received: by mail-qk1-x733.google.com with SMTP id af79cd13be357-7624af57b21so59479185a.1 for ; Fri, 23 Jun 2023 07:41:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1687531271; x=1690123271; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=7JaTTX/u6r9WHG8CBb2nIc/77Q7Cm1gWqR+xNarEVL8=; b=I+viCJg201Gtd7ZT+P2U7TbN5jygxO/f53vLkGn3QZ7W1uN/olak2ftuV3CJq/3eWS byqH6UFKNIHvjQLhQRItIRIGC6mGaGvZaemuuCNW/Lyo3FEQR7soYjUyEQTMjObhaDnQ Ug0vdxAX0lthxd4068ypa280pgcitnpN46qEk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687531271; x=1690123271; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=7JaTTX/u6r9WHG8CBb2nIc/77Q7Cm1gWqR+xNarEVL8=; b=gEgPHGWV8x2NrVKUkpNZfOV3tosPVgCGw3XB6a0ZDRBMBC9yUoweSTfn0N85eZA8Ua qIu+R8le9fthw4l8ut5/3+lFNruRwIdhQbOmpoBkTYE7H8Rlrwi3SaFl4PqwsLT5Dw1g VetOAgmsbV8Q6XRJC0MrOoAhEatMxyIuo1GcoxX9S1ubCNfYS69aZrcVcERAMNMb06it WV63mjxXnaXqW3cDr6rU4SI5hQ6MBX6D7DR3XiM2FuY0OjjSkqoJqPTRuI/gYU8DWoaa 6q4afTZC2dRQuKJEUz9NS9Rw+tZqLvvdPLfRPAXx/lhz1vbmAGTRz//UY5kYsACX9mbg b8Jg== X-Gm-Message-State: AC+VfDyfxgVMGp15hI+J8+w4B/58yjUJLrQ/WKEQE/Dfv9F1ptJCjYll SyDRlTVKjIhzt3gT5AiNMoB0f6sPUOIs3NLvJtZEOV0FpKOOLXxvjRXtRH+RwthfMdNenlEKDLJ 8QfrupLHsJ+GnFVfGd4UqEbZ2uzydz/OgP0tou1tTF8mwdp1/Wh4aWoY4UzI5rRXgdBGwFHGr1f s4ZnSQYUr1ew== X-Google-Smtp-Source: ACHHUZ4VUTc2qoNcrsn8Qp7O9siw73GsqtGEpwTfEu0R/xUCLrc8O1bXbkl3FlCTdDU63D7TU7ARxg== X-Received: by 2002:a05:620a:8290:b0:763:98b4:e81f with SMTP id ox16-20020a05620a829000b0076398b4e81fmr14356285qkn.39.1687531270963; Fri, 23 Jun 2023 07:41:10 -0700 (PDT) Received: from stbsrv-and-01.and.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id i18-20020a05620a145200b007625382f4ccsm4564613qkl.69.2023.06.23.07.41.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Jun 2023 07:41:10 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , Cyril Brulebois , Phil Elwell , bcm-kernel-feedback-list@broadcom.com, james.quinlan@broadcom.com Cc: Florian Fainelli , Jim Quinlan , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v6 3/5] PCI: brcmstb: Set higher value for internal bus timeout Date: Fri, 23 Jun 2023 10:40:56 -0400 Message-Id: <20230623144100.34196-4-james.quinlan@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230623144100.34196-1-james.quinlan@broadcom.com> References: <20230623144100.34196-1-james.quinlan@broadcom.com> X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, MIME_HEADER_CTYPE_ONLY,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_NONE, T_SCC_BODY_TEXT_LINE,T_TVD_MIME_NO_HEADERS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org During long periods of the PCIe RC HW being in an L1SS sleep state, there may be a timeout on an internal bus access, even though there may not be any PCIe access involved. Such a timeout will cause a subsequent CPU abort. So, when "brcm,enable-l1ss" is observed, we increase the timeout value to four seconds instead of using its HW default. Signed-off-by: Jim Quinlan Tested-by: Florian Fainelli --- drivers/pci/controller/pcie-brcmstb.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c index d30636a725d7..fe0415a98c63 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -1034,6 +1034,21 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) return 0; } +/* + * This extends the timeout period for an access to an internal bus. This + * access timeout may occur during L1SS sleep periods even without the + * presence of a PCIe access. + */ +static void brcm_extend_rbus_timeout(struct brcm_pcie *pcie) +{ + /* TIMEOUT register is two registers before RGR1_SW_INIT_1 */ + const unsigned int REG_OFFSET = PCIE_RGR1_SW_INIT_1(pcie) - 8; + u32 timeout_us = 4000000; /* 4 seconds, our setting for L1SS */ + + /* Each unit in timeout register is 1/216,000,000 seconds */ + writel(216 * timeout_us, pcie->base + REG_OFFSET); +} + static void brcm_config_clkreq(struct brcm_pcie *pcie) { bool l1ss = of_property_read_bool(pcie->np, "brcm,enable-l1ss"); @@ -1059,6 +1074,7 @@ static void brcm_config_clkreq(struct brcm_pcie *pcie) * of 400ns, as specified in 3.2.5.2.2 of the PCI Express * Mini CEM 2.0 specification. */ + brcm_extend_rbus_timeout(pcie); clkreq_set |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_L1SS_ENABLE_MASK; dev_info(pcie->dev, "bi-dir CLKREQ# for L1SS power savings"); } else {