From patchwork Tue Apr 18 07:46:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rick Wertenbroek X-Patchwork-Id: 1769976 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20221208 header.b=VvPmODTR; dkim-atps=neutral Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4Q0wyW0H6kz1yZr for ; Tue, 18 Apr 2023 17:48:19 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231251AbjDRHsO (ORCPT ); Tue, 18 Apr 2023 03:48:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55174 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230526AbjDRHsK (ORCPT ); Tue, 18 Apr 2023 03:48:10 -0400 Received: from mail-ej1-x630.google.com (mail-ej1-x630.google.com [IPv6:2a00:1450:4864:20::630]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 30D6B76A5; Tue, 18 Apr 2023 00:47:50 -0700 (PDT) Received: by mail-ej1-x630.google.com with SMTP id a5so14292586ejb.6; Tue, 18 Apr 2023 00:47:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1681804068; x=1684396068; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LB/hBZR8yZjvvma1XgK2soZdHK9U46eqjW0k2u2qdaw=; b=VvPmODTRSWxRQw4z5PuphOXjk9QKXdVuOolVhs0pLbWpGo5OrxV1SiE/G7BVu39CLc SFeHjPqqce1UwUjn8luF8/WxJ3kkJgdgiWP/T7S1MDpiO2rxruY4dyRzOxj3Vhb0YJjc uJoWIIyQKVFjrR9ORY72jCos/xlMCdkZ9wsQyBm1pwZJxYIqbwvA9FSUNwydHZoOl6An hdU+tBwtgJZz0Kwm0Nyl/PZthI/X2I4rK84fKwNDpzmSZ0gVt+yLjAoLYvVycGq97l7q YD5K0nYhfHIHdLY13LvrsfNZ6rjUNqlv5FqbMPBoyydFC/j0OmW9gaeUtXjcSapjxIVr i0Lg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681804068; x=1684396068; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LB/hBZR8yZjvvma1XgK2soZdHK9U46eqjW0k2u2qdaw=; b=FrhNR89SKhmC+g5WJe1RxmhKt38jUuLHN/dCsjcwOjT6nGGA0UTi1lJD/Th1UJCUi2 gHMeO6YBg9jN3DUY50W6MBflaOfZkGiD1WS7piMq5Jlu1cjrBjDs4HqUXxtxlX/br9OM hAMQAQesCTOV2eb9Os1ehPXiwBYqN16hpvbIXwTfomiQPTiBWJfKvUlB0Pwoy36lkBTO F6ej3F8qFnsvRhWfobdUot0vW3Ep1CTBoBSZm4qXPQhAvIEqKJRzMbDSeLGopje+ZJEw GCkCSrgWw1bN1X1cmGfkV2/3Nm3N05FBHlW07IWtoftMC1OlpuAuISSCY5hUE+1/12FT i4dA== X-Gm-Message-State: AAQBX9cQxKOv1YjUnK0ibnJNxA/QpNlqalCiS4Ni5ZC+7lx7S22xOjBK CAUwnAWuj4i2QNPgdVWwggM= X-Google-Smtp-Source: AKy350aYQU0ctOk0PyP74jWCcA9w/O/pwliRjBYZUKfvc0UrcfFPuvvj54f9Lt7AKK2eUMbuFoUQ8A== X-Received: by 2002:a17:906:350d:b0:94a:8f3a:1a77 with SMTP id r13-20020a170906350d00b0094a8f3a1a77mr9390578eja.8.1681804068555; Tue, 18 Apr 2023 00:47:48 -0700 (PDT) Received: from A13PC04R.einet.ad.eivd.ch ([193.134.219.72]) by smtp.googlemail.com with ESMTPSA id gs8-20020a1709072d0800b0094f694e4ecbsm3048545ejc.146.2023.04.18.00.47.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Apr 2023 00:47:48 -0700 (PDT) From: Rick Wertenbroek To: alberto.dassatti@heig-vd.ch Cc: xxm@rock-chips.com, dlemoal@kernel.org, Rick Wertenbroek , stable@vger.kernel.org, Shawn Lin , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Heiko Stuebner , Caleb Connolly , Brian Norris , Corentin Labbe , Johan Jonker , Hugh Cole-Baker , Judy Hsiao , Arnaud Ferraris , linux-pci@vger.kernel.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 02/11] PCI: rockchip: Write PCI Device ID to correct register Date: Tue, 18 Apr 2023 09:46:49 +0200 Message-Id: <20230418074700.1083505-3-rick.wertenbroek@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230418074700.1083505-1-rick.wertenbroek@gmail.com> References: <20230418074700.1083505-1-rick.wertenbroek@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Write PCI Device ID (DID) to the correct register. The Device ID was not updated through the correct register. Device ID was written to a read-only register and therefore did not work. The Device ID is now set through the correct register. This is documented in the RK3399 TRM section 17.6.6.1.1 Fixes: cf590b078391 ("PCI: rockchip: Add EP driver for Rockchip PCIe controller") Cc: stable@vger.kernel.org Reviewed-by: Damien Le Moal Tested-by: Damien Le Moal Signed-off-by: Rick Wertenbroek --- drivers/pci/controller/pcie-rockchip-ep.c | 6 ++++-- drivers/pci/controller/pcie-rockchip.h | 2 ++ 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c index d5c477020417..9b835377bd9e 100644 --- a/drivers/pci/controller/pcie-rockchip-ep.c +++ b/drivers/pci/controller/pcie-rockchip-ep.c @@ -115,6 +115,7 @@ static void rockchip_pcie_prog_ep_ob_atu(struct rockchip_pcie *rockchip, u8 fn, static int rockchip_pcie_ep_write_header(struct pci_epc *epc, u8 fn, u8 vfn, struct pci_epf_header *hdr) { + u32 reg; struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); struct rockchip_pcie *rockchip = &ep->rockchip; @@ -127,8 +128,9 @@ static int rockchip_pcie_ep_write_header(struct pci_epc *epc, u8 fn, u8 vfn, PCIE_CORE_CONFIG_VENDOR); } - rockchip_pcie_write(rockchip, hdr->deviceid << 16, - ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + PCI_VENDOR_ID); + reg = rockchip_pcie_read(rockchip, PCIE_EP_CONFIG_DID_VID); + reg = (reg & 0xFFFF) | (hdr->deviceid << 16); + rockchip_pcie_write(rockchip, reg, PCIE_EP_CONFIG_DID_VID); rockchip_pcie_write(rockchip, hdr->revid | diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h index 32c3a859c26b..51a123e5c0cf 100644 --- a/drivers/pci/controller/pcie-rockchip.h +++ b/drivers/pci/controller/pcie-rockchip.h @@ -133,6 +133,8 @@ #define PCIE_RC_RP_ATS_BASE 0x400000 #define PCIE_RC_CONFIG_NORMAL_BASE 0x800000 #define PCIE_RC_CONFIG_BASE 0xa00000 +#define PCIE_EP_CONFIG_BASE 0xa00000 +#define PCIE_EP_CONFIG_DID_VID (PCIE_EP_CONFIG_BASE + 0x00) #define PCIE_RC_CONFIG_RID_CCR (PCIE_RC_CONFIG_BASE + 0x08) #define PCIE_RC_CONFIG_DCR (PCIE_RC_CONFIG_BASE + 0xc4) #define PCIE_RC_CONFIG_DCR_CSPL_SHIFT 18