| Message ID | 20221110183158.856242-2-dmitry.baryshkov@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | PCI/phy: Add support for PCI on sm8350 platform | expand |
On 10/11/2022 19:31, Dmitry Baryshkov wrote: > Add bindings for two PCIe hosts on SM8350 platform. The only difference > between them is in the aggre0 clock, which warrants the oneOf clause for > the clocks properties. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > .../devicetree/bindings/pci/qcom,pcie.yaml | 46 +++++++++++++++++++ > 1 file changed, 46 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > index 54f07852d279..502c15f7dd96 100644 > --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > @@ -32,6 +32,7 @@ properties: > - qcom,pcie-sdm845 > - qcom,pcie-sm8150 > - qcom,pcie-sm8250 > + - qcom,pcie-sm8350 > - qcom,pcie-sm8450-pcie0 > - qcom,pcie-sm8450-pcie1 > - qcom,pcie-ipq6018 > @@ -185,6 +186,7 @@ allOf: > - qcom,pcie-sc8180x > - qcom,pcie-sc8280xp > - qcom,pcie-sm8250 > + - qcom,pcie-sm8350 > - qcom,pcie-sm8450-pcie0 > - qcom,pcie-sm8450-pcie1 > then: > @@ -540,6 +542,49 @@ allOf: > items: > - const: pci # PCIe core reset > > + - if: > + properties: > + compatible: > + contains: > + enum: > + - qcom,pcie-sm8350 > + then: > + oneOf: > + # Unfortunately the "optional" aggre0 clock is used in the middle of the list It's a new device, new support, so you can put it everywhere you wish, can't you? Just put at the and and add minItems:8 Best regards, Krzysztof
On Thu, Nov 10, 2022 at 09:31:51PM +0300, Dmitry Baryshkov wrote: > Add bindings for two PCIe hosts on SM8350 platform. The only difference > between them is in the aggre0 clock, which warrants the oneOf clause for > the clocks properties. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > .../devicetree/bindings/pci/qcom,pcie.yaml | 46 +++++++++++++++++++ > 1 file changed, 46 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > index 54f07852d279..502c15f7dd96 100644 > --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > @@ -32,6 +32,7 @@ properties: > - qcom,pcie-sdm845 > - qcom,pcie-sm8150 > - qcom,pcie-sm8250 > + - qcom,pcie-sm8350 > - qcom,pcie-sm8450-pcie0 > - qcom,pcie-sm8450-pcie1 > - qcom,pcie-ipq6018 > @@ -185,6 +186,7 @@ allOf: > - qcom,pcie-sc8180x > - qcom,pcie-sc8280xp > - qcom,pcie-sm8250 > + - qcom,pcie-sm8350 > - qcom,pcie-sm8450-pcie0 > - qcom,pcie-sm8450-pcie1 > then: > @@ -540,6 +542,49 @@ allOf: > items: > - const: pci # PCIe core reset > > + - if: > + properties: > + compatible: > + contains: > + enum: > + - qcom,pcie-sm8350 > + then: > + oneOf: > + # Unfortunately the "optional" aggre0 clock is used in the middle of the list As Krzysztof mentioned, you can just move it last (and the driver will still enable aggre0 before aggre1 if that's a concern). > + - properties: > + clocks: > + maxItems: 9 > + clock-names: > + items: > + - const: aux # Auxiliary clock > + - const: cfg # Configuration clock > + - const: bus_master # Master AXI clock > + - const: bus_slave # Slave AXI clock > + - const: slave_q2a # Slave Q2A clock > + - const: tbu # PCIe TBU clock > + - const: ddrss_sf_tbu # PCIe SF TBU clock > + - const: aggre0 # Aggre NoC PCIe0 AXI clock > + - const: aggre1 # Aggre NoC PCIe1 AXI clock Have you verified that you actually need the bus clock for the second controller here? > + - properties: > + clocks: > + maxItems: 8 > + clock-names: > + items: > + - const: aux # Auxiliary clock > + - const: cfg # Configuration clock > + - const: bus_master # Master AXI clock > + - const: bus_slave # Slave AXI clock > + - const: slave_q2a # Slave Q2A clock > + - const: tbu # PCIe TBU clock > + - const: ddrss_sf_tbu # PCIe SF TBU clock > + - const: aggre1 # Aggre NoC PCIe1 AXI clock > + properties: > + resets: > + maxItems: 1 > + reset-names: > + items: > + - const: pci # PCIe core reset > + Johan
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 54f07852d279..502c15f7dd96 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -32,6 +32,7 @@ properties: - qcom,pcie-sdm845 - qcom,pcie-sm8150 - qcom,pcie-sm8250 + - qcom,pcie-sm8350 - qcom,pcie-sm8450-pcie0 - qcom,pcie-sm8450-pcie1 - qcom,pcie-ipq6018 @@ -185,6 +186,7 @@ allOf: - qcom,pcie-sc8180x - qcom,pcie-sc8280xp - qcom,pcie-sm8250 + - qcom,pcie-sm8350 - qcom,pcie-sm8450-pcie0 - qcom,pcie-sm8450-pcie1 then: @@ -540,6 +542,49 @@ allOf: items: - const: pci # PCIe core reset + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-sm8350 + then: + oneOf: + # Unfortunately the "optional" aggre0 clock is used in the middle of the list + - properties: + clocks: + maxItems: 9 + clock-names: + items: + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: tbu # PCIe TBU clock + - const: ddrss_sf_tbu # PCIe SF TBU clock + - const: aggre0 # Aggre NoC PCIe0 AXI clock + - const: aggre1 # Aggre NoC PCIe1 AXI clock + - properties: + clocks: + maxItems: 8 + clock-names: + items: + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: tbu # PCIe TBU clock + - const: ddrss_sf_tbu # PCIe SF TBU clock + - const: aggre1 # Aggre NoC PCIe1 AXI clock + properties: + resets: + maxItems: 1 + reset-names: + items: + - const: pci # PCIe core reset + - if: properties: compatible: @@ -670,6 +715,7 @@ allOf: - qcom,pcie-sdm845 - qcom,pcie-sm8150 - qcom,pcie-sm8250 + - qcom,pcie-sm8350 - qcom,pcie-sm8450-pcie0 - qcom,pcie-sm8450-pcie1 then:
Add bindings for two PCIe hosts on SM8350 platform. The only difference between them is in the aggre0 clock, which warrants the oneOf clause for the clocks properties. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- .../devicetree/bindings/pci/qcom,pcie.yaml | 46 +++++++++++++++++++ 1 file changed, 46 insertions(+)