| Message ID | 20221101052049.3946283-1-thippeswamy.havalige@amd.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v2,1/2] dt-bindings: PCI: xilinx-pcie: Convert to YAML schemas of Xilinx AXI PCIe Root Port Bridge | expand |
On Tue, Nov 01, 2022 at 10:50:48AM +0530, Thippeswamy Havalige wrote: > Convert to YAML dtschemas of Xilinx AXI PCIe Root Port Bridge > dt binding. > > Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com> > --- > .../devicetree/bindings/pci/xilinx-pcie.txt | 88 ------------------- > .../bindings/pci/xlnx,axi-pcie-host.yaml | 87 ++++++++++++++++++ > 2 files changed, 87 insertions(+), 88 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/pci/xilinx-pcie.txt > create mode 100644 Documentation/devicetree/bindings/pci/xlnx,axi-pcie-host.yaml > > diff --git a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt > deleted file mode 100644 > index fd57a81180a4..000000000000 > --- a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt > +++ /dev/null > @@ -1,88 +0,0 @@ > -* Xilinx AXI PCIe Root Port Bridge DT description > - > -Required properties: > -- #address-cells: Address representation for root ports, set to <3> > -- #size-cells: Size representation for root ports, set to <2> > -- #interrupt-cells: specifies the number of cells needed to encode an > - interrupt source. The value must be 1. > -- compatible: Should contain "xlnx,axi-pcie-host-1.00.a" > -- reg: Should contain AXI PCIe registers location and length > -- device_type: must be "pci" > -- interrupts: Should contain AXI PCIe interrupt > -- interrupt-map-mask, > - interrupt-map: standard PCI properties to define the mapping of the > - PCI interface to interrupt numbers. > -- ranges: ranges for the PCI memory regions (I/O space region is not > - supported by hardware) > - Please refer to the standard PCI bus binding document for a more > - detailed explanation > - > -Optional properties for Zynq/Microblaze: > -- bus-range: PCI bus numbers covered > - > -Interrupt controller child node > -+++++++++++++++++++++++++++++++ > -Required properties: > -- interrupt-controller: identifies the node as an interrupt controller > -- #address-cells: specifies the number of cells needed to encode an > - address. The value must be 0. > -- #interrupt-cells: specifies the number of cells needed to encode an > - interrupt source. The value must be 1. > - > -NOTE: > -The core provides a single interrupt for both INTx/MSI messages. So, > -created a interrupt controller node to support 'interrupt-map' DT > -functionality. The driver will create an IRQ domain for this map, decode > -the four INTx interrupts in ISR and route them to this domain. > - > - > -Example: > -++++++++ > -Zynq: > - pci_express: axi-pcie@50000000 { > - #address-cells = <3>; > - #size-cells = <2>; > - #interrupt-cells = <1>; > - compatible = "xlnx,axi-pcie-host-1.00.a"; > - reg = < 0x50000000 0x1000000 >; > - device_type = "pci"; > - interrupts = < 0 52 4 >; > - interrupt-map-mask = <0 0 0 7>; > - interrupt-map = <0 0 0 1 &pcie_intc 1>, > - <0 0 0 2 &pcie_intc 2>, > - <0 0 0 3 &pcie_intc 3>, > - <0 0 0 4 &pcie_intc 4>; > - ranges = < 0x02000000 0 0x60000000 0x60000000 0 0x10000000 >; > - > - pcie_intc: interrupt-controller { > - interrupt-controller; > - #address-cells = <0>; > - #interrupt-cells = <1>; > - }; > - }; > - > - > -Microblaze: > - pci_express: axi-pcie@10000000 { > - #address-cells = <3>; > - #size-cells = <2>; > - #interrupt-cells = <1>; > - compatible = "xlnx,axi-pcie-host-1.00.a"; > - reg = <0x10000000 0x4000000>; > - device_type = "pci"; > - interrupt-parent = <µblaze_0_intc>; > - interrupts = <1 2>; > - interrupt-map-mask = <0 0 0 7>; > - interrupt-map = <0 0 0 1 &pcie_intc 1>, > - <0 0 0 2 &pcie_intc 2>, > - <0 0 0 3 &pcie_intc 3>, > - <0 0 0 4 &pcie_intc 4>; > - ranges = <0x02000000 0x00000000 0x80000000 0x80000000 0x00000000 0x10000000>; > - > - pcie_intc: interrupt-controller { > - interrupt-controller; > - #address-cells = <0>; > - #interrupt-cells = <1>; > - }; > - > - }; > diff --git a/Documentation/devicetree/bindings/pci/xlnx,axi-pcie-host.yaml b/Documentation/devicetree/bindings/pci/xlnx,axi-pcie-host.yaml > new file mode 100644 > index 000000000000..fc0761a7a2e2 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pci/xlnx,axi-pcie-host.yaml > @@ -0,0 +1,87 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pci/xlnx,axi-pcie-host.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Xilinx AXI PCIe Root Port Bridge > + > +maintainers: > + - Thippeswamy Havalige <thippeswamy.havalige@amd.com> > + > +allOf: > + - $ref: /schemas/pci/pci-bus.yaml# > + > +properties: > + compatible: > + const: xlnx,axi-pcie-host-1.00.a > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + ranges: > + items: > + - description: | > + ranges for the PCI memory regions (I/O space region is not > + supported by hardware) > + > + "#interrupt-cells": > + const: 1 > + > + interrupt-controller: > + description: identifies the node as an interrupt controller > + type: object additionalProperties: false > + properties: > + "interrupt-controller": true Don't need quotes. > + "#address-cells": > + const: 0 blank line > + "#interrupt-cells": > + const: 1 > + > + required: > + - 'interrupt-controller' > + - '#address-cells' > + - '#interrupt-cells' > + > + additionalProperties: false > + > +required: > + - compatible > + - reg > + - ranges > + - interrupts > + - interrupt-map > + - "#interrupt-cells" > + - interrupt-controller > + > +unevaluatedProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/interrupt-controller/irq.h> > + > + zynq: Odd, but I guess a valid label because they can appear about anywhere or multiple labels in the same place. Drop and adjust the indentation. > + pci_express: pcie@50000000 { Drop unused labels. > + compatible = "xlnx,axi-pcie-host-1.00.a"; > + reg = < 0x50000000 0x1000000 >; > + #address-cells = <3>; > + #size-cells = <2>; > + #interrupt-cells = <1>; > + device_type = "pci"; > + interrupts = < GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH >; > + interrupt-map-mask = <0 0 0 7>; > + interrupt-map = <0 0 0 1 &pcie_intc 1>, > + <0 0 0 2 &pcie_intc 2>, > + <0 0 0 3 &pcie_intc 3>, > + <0 0 0 4 &pcie_intc 4>; > + ranges = < 0x02000000 0 0x60000000 0x60000000 0 0x10000000 >; > + pcie_intc: interrupt-controller { > + interrupt-controller; > + #address-cells = <0>; > + #interrupt-cells = <1>; > + }; > + }; > -- > 2.25.1 > >
diff --git a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt deleted file mode 100644 index fd57a81180a4..000000000000 --- a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt +++ /dev/null @@ -1,88 +0,0 @@ -* Xilinx AXI PCIe Root Port Bridge DT description - -Required properties: -- #address-cells: Address representation for root ports, set to <3> -- #size-cells: Size representation for root ports, set to <2> -- #interrupt-cells: specifies the number of cells needed to encode an - interrupt source. The value must be 1. -- compatible: Should contain "xlnx,axi-pcie-host-1.00.a" -- reg: Should contain AXI PCIe registers location and length -- device_type: must be "pci" -- interrupts: Should contain AXI PCIe interrupt -- interrupt-map-mask, - interrupt-map: standard PCI properties to define the mapping of the - PCI interface to interrupt numbers. -- ranges: ranges for the PCI memory regions (I/O space region is not - supported by hardware) - Please refer to the standard PCI bus binding document for a more - detailed explanation - -Optional properties for Zynq/Microblaze: -- bus-range: PCI bus numbers covered - -Interrupt controller child node -+++++++++++++++++++++++++++++++ -Required properties: -- interrupt-controller: identifies the node as an interrupt controller -- #address-cells: specifies the number of cells needed to encode an - address. The value must be 0. -- #interrupt-cells: specifies the number of cells needed to encode an - interrupt source. The value must be 1. - -NOTE: -The core provides a single interrupt for both INTx/MSI messages. So, -created a interrupt controller node to support 'interrupt-map' DT -functionality. The driver will create an IRQ domain for this map, decode -the four INTx interrupts in ISR and route them to this domain. - - -Example: -++++++++ -Zynq: - pci_express: axi-pcie@50000000 { - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - compatible = "xlnx,axi-pcie-host-1.00.a"; - reg = < 0x50000000 0x1000000 >; - device_type = "pci"; - interrupts = < 0 52 4 >; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc 1>, - <0 0 0 2 &pcie_intc 2>, - <0 0 0 3 &pcie_intc 3>, - <0 0 0 4 &pcie_intc 4>; - ranges = < 0x02000000 0 0x60000000 0x60000000 0 0x10000000 >; - - pcie_intc: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - }; - - -Microblaze: - pci_express: axi-pcie@10000000 { - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - compatible = "xlnx,axi-pcie-host-1.00.a"; - reg = <0x10000000 0x4000000>; - device_type = "pci"; - interrupt-parent = <µblaze_0_intc>; - interrupts = <1 2>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc 1>, - <0 0 0 2 &pcie_intc 2>, - <0 0 0 3 &pcie_intc 3>, - <0 0 0 4 &pcie_intc 4>; - ranges = <0x02000000 0x00000000 0x80000000 0x80000000 0x00000000 0x10000000>; - - pcie_intc: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - - }; diff --git a/Documentation/devicetree/bindings/pci/xlnx,axi-pcie-host.yaml b/Documentation/devicetree/bindings/pci/xlnx,axi-pcie-host.yaml new file mode 100644 index 000000000000..fc0761a7a2e2 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/xlnx,axi-pcie-host.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/xlnx,axi-pcie-host.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx AXI PCIe Root Port Bridge + +maintainers: + - Thippeswamy Havalige <thippeswamy.havalige@amd.com> + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + +properties: + compatible: + const: xlnx,axi-pcie-host-1.00.a + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + ranges: + items: + - description: | + ranges for the PCI memory regions (I/O space region is not + supported by hardware) + + "#interrupt-cells": + const: 1 + + interrupt-controller: + description: identifies the node as an interrupt controller + type: object + properties: + "interrupt-controller": true + "#address-cells": + const: 0 + "#interrupt-cells": + const: 1 + + required: + - 'interrupt-controller' + - '#address-cells' + - '#interrupt-cells' + + additionalProperties: false + +required: + - compatible + - reg + - ranges + - interrupts + - interrupt-map + - "#interrupt-cells" + - interrupt-controller + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + + zynq: + pci_express: pcie@50000000 { + compatible = "xlnx,axi-pcie-host-1.00.a"; + reg = < 0x50000000 0x1000000 >; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + interrupts = < GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH >; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc 1>, + <0 0 0 2 &pcie_intc 2>, + <0 0 0 3 &pcie_intc 3>, + <0 0 0 4 &pcie_intc 4>; + ranges = < 0x02000000 0 0x60000000 0x60000000 0 0x10000000 >; + pcie_intc: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + };
Convert to YAML dtschemas of Xilinx AXI PCIe Root Port Bridge dt binding. Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com> --- .../devicetree/bindings/pci/xilinx-pcie.txt | 88 ------------------- .../bindings/pci/xlnx,axi-pcie-host.yaml | 87 ++++++++++++++++++ 2 files changed, 87 insertions(+), 88 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pci/xilinx-pcie.txt create mode 100644 Documentation/devicetree/bindings/pci/xlnx,axi-pcie-host.yaml