@@ -103,24 +103,6 @@ static inline int isa_vaddr_is_ioport(void __iomem *address)
}
#endif /* CONFIG_PCI */
-/* These are used for config access before all the PCI probing
- has been done. */
-extern int early_read_config_byte(struct pci_controller *hose, int bus,
- int dev_fn, int where, u8 *val);
-extern int early_read_config_word(struct pci_controller *hose, int bus,
- int dev_fn, int where, u16 *val);
-extern int early_read_config_dword(struct pci_controller *hose, int bus,
- int dev_fn, int where, u32 *val);
-extern int early_write_config_byte(struct pci_controller *hose, int bus,
- int dev_fn, int where, u8 val);
-extern int early_write_config_word(struct pci_controller *hose, int bus,
- int dev_fn, int where, u16 val);
-extern int early_write_config_dword(struct pci_controller *hose, int bus,
- int dev_fn, int where, u32 val);
-
-extern int early_find_capability(struct pci_controller *hose, int bus,
- int dev_fn, int cap);
-
extern void setup_indirect_pci(struct pci_controller *hose,
resource_size_t cfg_addr,
resource_size_t cfg_data, u32 flags);
@@ -1060,8 +1060,3 @@ long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn)
EARLY_PCI_OP(write, word, u16)
EARLY_PCI_OP(write, dword, u32)
-int early_find_capability(struct pci_controller *hose, int bus, int devfn,
- int cap)
-{
- return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
-}
@@ -76,44 +76,6 @@ static void xilinx_pci_fixup_bridge(struct pci_dev *dev)
{
return (bus != 0);
}
-
-/**
- * xilinx_early_pci_scan - List pci config space for available devices
- *
- * List pci devices in very early phase.
- */
-static void __init xilinx_early_pci_scan(struct pci_controller *hose)
-{
- u32 bus = 0;
- u32 val, dev, func, offset;
-
- /* Currently we have only 2 device connected - up-to 32 devices */
- for (dev = 0; dev < 2; dev++) {
- /* List only first function number - up-to 8 functions */
- for (func = 0; func < 1; func++) {
- pr_info("%02x:%02x:%02x", bus, dev, func);
- /* read the first 64 standardized bytes */
- /* Up-to 192 bytes can be list of capabilities */
- for (offset = 0; offset < 64; offset += 4) {
- early_read_config_dword(hose, bus,
- PCI_DEVFN(dev, func), offset, &val);
- if (offset == 0 && val == 0xFFFFFFFF) {
- pr_cont("\nABSENT");
- break;
- }
- if (!(offset % 0x10))
- pr_cont("\n%04x: ", offset);
-
- pr_cont("%08x ", val);
- }
- pr_info("\n");
- }
- }
-}
-#else
-static void __init xilinx_early_pci_scan(struct pci_controller *hose)
-{
-}
#endif
/**
@@ -146,15 +108,6 @@ void __init xilinx_pci_init(void)
r.start + XPLB_PCI_DATA,
INDIRECT_TYPE_SET_CFG_TYPE);
- /* According to the xilinx plbv46_pci documentation the soft-core starts
- * a self-init when the bus master enable bit is set. Without this bit
- * set the pci bus can't be scanned.
- */
- early_write_config_word(hose, 0, 0, PCI_COMMAND, PCI_HOST_ENABLE_CMD);
-
- /* Set the max latency timer to 255 */
- early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0xff);
-
/* Set the max bus number to 255, and bus/subbus no's to 0 */
pci_reg = of_iomap(pci_node, 0);
WARN_ON(!pci_reg);
@@ -166,5 +119,4 @@ void __init xilinx_pci_init(void)
INDIRECT_TYPE_SET_CFG_TYPE);
pr_info("xilinx-pci: Registered PCI host bridge\n");
- xilinx_early_pci_scan(hose);
}
early_read_config_byte() and similar are declared but never defined. Remove the unused declarations. Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com> --- arch/microblaze/include/asm/pci-bridge.h | 18 ------------ arch/microblaze/pci/pci-common.c | 5 ---- arch/microblaze/pci/xilinx_pci.c | 48 -------------------------------- 3 files changed, 71 deletions(-)